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Journal ArticleDOI

A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS

01 Dec 2001-Vol. 36, Iss: 12, pp 1847-1858
TL;DR: In this paper, a 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz using array averaging and a wideband track-and-hold is reported.
Abstract: A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.
Citations
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Journal ArticleDOI
TL;DR: This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.
Abstract: The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

324 citations

Journal ArticleDOI
16 Dec 2002
TL;DR: A 1.6 Gsample/s 6b flash analog-to-digital converter in 0.18 /spl mu/m CMOS is for storage read channels, which achieves 5.7 effective bits at DC and 5 effectivebits at 660 MHz.
Abstract: The output averaging technique for input amplifiers of a flash ADC has been analyzed mathematically. Expressions have been derived for the reduction of differential nonlinearity, integral nonlinearity, and the necessary number of overrange amplifiers as a function of the output and averaging resistors. This theory is applied to design a 1.6-Gigasample/s 6-b flash ADC in baseline 0.18-/spl mu/m CMOS technology. A distributed track and hold is implemented to achieve a high sample rate. The small input signal is amplified through a cascade of amplifiers and gradually transformed into robust digital signal levels. An averaging termination circuit has been designed to resemble the infinite string of resistors and amplifiers. By applying termination to the averaging network, the amount of overrange amplifiers and, therefore, the power consumption is reduced, while the linearity and speed performance are maintained. The optimum number of parallel pre-amplifiers is derived on the basis of the tradeoff between the amplifier offset and distortion.

176 citations


Cites background from "A 6 b 1.3 GSample/s A/D converter i..."

  • ...Recent publications show a need for 6 overrange amplifiers in case of a 16-amplifier-wide array and up to 18 overrange amplifiers in case of a 63-amplifier-wide array [2,3]....

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Journal ArticleDOI
TL;DR: A 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology, and achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power.
Abstract: We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GS/s the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MS/s we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.

174 citations

Journal ArticleDOI
TL;DR: The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented and an extensive description of the implemented digital error correction technique is described.
Abstract: The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm/sup 2/. The ADC is implemented in a 0.25-/spl mu/m pure digital CMOS technology.

166 citations

Journal ArticleDOI
TL;DR: In this article, the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters is reviewed with respect to technology scaling, and a comparison is made between slew-rate dominated circuits and settling dominated circuits.
Abstract: In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit.

140 citations

References
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Journal ArticleDOI
TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >

3,121 citations

Journal ArticleDOI
TL;DR: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.
Abstract: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

849 citations

Journal ArticleDOI
TL;DR: The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta ( Sigma Delta ) modulation and applies these criteria to the design of a modulator that has been integrated in a 3- mu m CMOS technology.
Abstract: The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta ( Sigma Delta ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Sigma 2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3- mu m CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm/sup 2/, and has achieved a measured dynamic range of 89 dB. >

779 citations

Journal ArticleDOI
TL;DR: It is shown that this easy-to-handle simplified model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.
Abstract: Charge injection in MOS analog switches, also called pass transistors or transmission gates, is approached by using the continuity equation. Experimental results show the negligible influence of substrate current which leads to a unidimensional model. An easy-to-handle simplified model is deduced and its predictions compared to the injection obtained by measurements. It is shown that this model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.

363 citations

Journal ArticleDOI
TL;DR: In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
Abstract: New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

270 citations