A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process
TL;DR: A 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process can help overcome some of the constraints imposed by nanometerCMOS process for high performance analog circuits in weak inversion region.
Abstract: This paper presents a 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process. The amplifier operates in the weak-inversion region with input bulk-driven differential pair sporting positive feedback source degeneration for transconductance enhancement. In addition, the distributed layout configuration is used for all the transistors to mitigate the effect of halo implants for higher output impedance. Combining these two approaches, we experimentally demonstrate a high gain of over 60-dB with just 18-nW power consumption from 0.25-V power supply. The use of enhanced bulk-driven differential pair and distributed layout can help overcome some of the constraints imposed by nanometer CMOS process for high performance analog circuits in weak inversion region.
Citations
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TL;DR: Overall good large-Signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
Abstract: A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.
100 citations
TL;DR: Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance and design feasibility under ultra-low-voltage conditions.
Abstract: An operational-transconductance-amplifier (OTA) design for ultra-low voltage ultra-low power applications is proposed. The input stage of the proposed OTA utilizes a bulk-driven pseudo-differential pair to allow minimum supply voltage while achieving a rail-to-rail input range. All the transistors in the proposed OTA operate in the subthreshold region. Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance of the OTA. The proposed technique ensures the OTA robustness to process variations and increases design feasibility under ultra-low-voltage conditions. Moreover, the proposed biasing technique significantly improves the common-mode and power-supply rejection of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping-factor control circuit is exploited. The OTA is fabricated in a 65 nm CMOS technology. Measurement results show that the OTA provides a low-frequency gain of 46 dB and rail-to-rail input common-mode range with a supply voltage as low as 0.5 V. The dc gain of the OTA is greater than 42 dB for supply voltage as low as 0.35 V. The power dissipation is 182 $\mu{\rm W}$ at $V_{DD}=0.5\ {\rm V}$ and 17 $\mu{\rm W}$ at $V_{DD}=0.35\ {\rm V}$ .
88 citations
70 citations
Cites background from "A 60-dB Gain OTA Operating at 0.25-..."
...FOMSV and FOMLV (as proposed in Ferreira and Sonkusale14) take into account also the relative ratio of the average |VTH| to the supply voltage VDD....
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TL;DR: A CMOS OTA in a 0.35- μm technology that occupies only 4.4·10-3 mm2, is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF, is designed.
Abstract: A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads Indeed, by following the presented methodology we designed a CMOS OTA in a 035- $\mu{\rm m}$ technology that occupies only $44\cdot 10^{-3}\ {\rm mm}^{2}$ , is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 ${\rm mV}/\mu{\rm s}$ with the 200 pF load Comparison with prior art shows an improvement factor in the figures of merit higher than 5
69 citations
TL;DR: A simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time.
Abstract: In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from $V_{\mathbf {DD}}$ ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.
53 citations
References
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TL;DR: In this paper, operational transconductance amplifier (OTA) and filter design for analog circuits with very low supply voltages, down to 0.5 V, are presented. But they do not consider the effect of low-voltage analog circuits on the performance.
Abstract: We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.
471 citations
03 Jan 2005
TL;DR: In this paper, the gate-leakage mismatch exceeds conventional matching tolerances, and the drop in supply voltages can solve this problem by exploiting combinations of thin and thick-oxide transistors.
Abstract: Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.
425 citations
TL;DR: In this article, a simple approach in the design of composite field effect transistors with low output conductance is presented, where the transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connecting to the source terminal.
Abstract: This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its "DC equivalent" transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays. >
227 citations
TL;DR: Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.
Abstract: An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion The improved Miller OTA has been successfully verified in a standard 035-mum CMOS process Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW
186 citations
TL;DR: A CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments is introduced, based on a bulk-driven input stage with extended input common-mode voltage range.
Abstract: This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output.
178 citations