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Proceedings ArticleDOI

A 60GHz, 13 dBm fully integrated 65nm RF-CMOS power amplifier

TL;DR: In this paper, a 65 nm CMOS, 60 GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low-cost Wireless Personal Area Network (WPAN).
Abstract: A 65 nm CMOS, 60 GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low cost Wireless Personal Area Network (WPAN). It has been optimized to deliver the maximum linear output power (OCP1) without using parallel amplification topology. The simulated OCP1 is equal to 8.9 dBm with a gain of 8 dB. To obtain good performances and consume an ultra compact area of silicon, the PA has been matched and optimized with a mixed technique, using lumped and distributed elements. The chip size is 0.48 mm*0.6 mm including pads.

Summary (2 min read)

INTRODUCTION

  • Communications systems are able to ensure 1-3 GBit/s for directional links using an ASK, PSK modulation, or using an Omni-directional link with OFDM modulation with a rate higher than 500Mbps [5] .
  • The 60GHz band is of special interest because of the attenuation (10 to 15dB/Km) due to vibrations of atmospheric oxygen molecules at this frequency.
  • Its high integration level and its low cost at high volumes are sufficient reasons to set aside the (III-V) semiconductor technology which is known as offering the best performance in gain, efficiency and output power.
  • Finally, the performances of the simulated PA will be presented and discussed.

II. CMOS TECHNOLOGY

  • The Power amplifier illustrated in this paper was designed with a 65nm CMOS on bulk (resistivity ρ=20mΩ.cm) from STMicroelectronics [7] .
  • Low power (LP) transistors were chosen as active devices.
  • They unfortunately have a lower tranconductance [4] .
  • There are several benefits from this scaling technology.
  • Indeed, the reduction of the gate resistance increases the gain and the power added efficiency (PAE).

III. SIMULATION METHODOLOGY

  • The principal reason of using this technology is the high f max and its capability to operate at 60GHz.
  • At this frequency, the authors have to take into account some other considerations, principally the electromagnetic effects, responsible for the degradation of performances.
  • Therefore, small and large analyses were done to characterize the circuit, especially the post layout simulation.

A. Transistor Layout Caracterisation

  • The size of the transistor depends on the maximum power defined by the user.
  • The authors must not forget that the relationship between these two parameters is not linear.
  • In fact, losses and the complexity of modeling increase with the size of the transistor.
  • This is mainly due to capacitive and inductive effects of routed elements and silicon substrate loss.
  • Thus, the authors must have a strong current to provide the power.

B. Transistor simulation

  • To perform this analysis, a microwave approach was necessary, also known as Small signal.
  • Accesses to gate, drain, and source were simulated with Ansoft HFSS electromagnetic simulator and represented by S-parameters blocks.
  • The overall system illustrated in Fig. 1 (a) was simulated in Cadence environment.
  • This took into account the effects of distributed elements and the influence of the ground return path.
  • A model with lumped elements is needed [9] and will be compared to the S-parameters mentioned above.

IV. CIRCUIT DESIGN

  • The output transistor is biased at the optimum linearity current density [10] of (70mA/200μm) whereas the driver favors the PA gain.
  • The first stage is biased by a tee polarization (LT, CT) outside the chip.
  • These lines measure up to λ/20 and can change the impedance.
  • Microstrip lines offer low characteristic impedance and hence consume a compact area of silicon.
  • Large signal simulations, at 60GHz, were performed in Cadence environment.

VI. CONCLUSION

  • A 65nm CMOS, 60GHz fully integrated power amplifier was designed and sent to STMicroelectronics foundry.
  • To perform small and large signal analysis, a microwave and system approaches were necessary.
  • These results can be improved by adding a third stage or using parallel amplification structure.

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Submitted on 6 Oct 2008
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A 60GHz, 13dBm Fully Integrated 65nm RF-CMOS
Power Amplier
Soane Aloui, Eric Kerherve, Didier Belot, Robert Plana
To cite this version:
Soane Aloui, Eric Kerherve, Didier Belot, Robert Plana. A 60GHz, 13dBm Fully Integrated 65nm
RF-CMOS Power Amplier. Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA
2008. 2008, Jun 2008, Montreal, Canada. �hal-00326811�

A 60GHz, 13dBm Fully Integrated 65nm RF-CMOS
Power Amplifier
Sofiane Aloui, Eric Kerhervé
IMS laboratory, UMR CNRS 5218
University of Bordeaux
33405 Talence Cedex, France
sofiane.aloui@ims-bordeaux.fr
Didier Belot
STMicroelectronics
Central R&D 1
Crolles, France
didier.belot@st.com
Robert Plana
LAAS-CNRS
University of Toulouse
Toulouse, France
plana@laas.fr
Abstract—A 65nm CMOS, 60GHz fully integrated power
amplifier (PA) from STMicroelectronics has been designed for
low cost Wireless Personal Area Network (WPAN). It has been
optimized to deliver the maximum linear output power (OCP1)
without using parallel amplification topology. The simulated
OCP1 is equal to 8.9 dBm with a gain of 8dB. To obtain good
performances and consume an ultra compact area of silicon,
the PA has been matched and optimized with a mixed
technique, using lumped and distributed elements. The chip
size is 0.48mm*0.6mm including pads.
I. INTRODUCTION
In the ISM band, a 7GHz unlicensed bandwidth around
60GHz is employed [1] [2] [3] [4]. Communications systems
are able to ensure 1-3 GBit/s for directional links using an
ASK, PSK modulation, or using an Omni-directional link
with OFDM modulation with a rate higher than 500Mbps
[5]. The 60GHz band is of special interest because of the
attenuation (10 to 15dB/Km) due to vibrations of
atmospheric oxygen molecules at this frequency. In this
respect, this band is suitable for short range communications
(distance < 10m), such as the indoor environment.
This application covers a big market, such as the
exchange of large files between wireless devices and also the
High Definition Television Video (HDTV) signal streaming
in WPAN network [6]. The CMOS technology was chosen
to reach these goals. Its high integration level and its low
cost at high volumes are sufficient reasons to set aside the
(III-V) semiconductor technology which is known as
offering the best performance in gain, efficiency and output
power.
In this paper, a fully integrated CMOS power amplifier is
reported. It operates in 57 to 63 GHz frequency range.
Initially, a brief description of the technology is provided.
Then, a modeling effort is made to forecast the response of
active and passive elements. This study will be concentrated
distinctly in small and large signal analysis. Finally, the
performances of the simulated PA will be presented and
discussed.
II. CMOS
TECHNOLOGY
The Power amplifier illustrated in this paper was
designed with a 65nm CMOS on bulk (resistivity
ρ=20m.cm) from STMicroelectronics [7]. Low power (LP)
transistors were chosen as active devices. They offer a cut-
off frequency F
t
and a maximum frequency of oscillation f
max
around, 200 and 250GHz respectively. Compared to the
general purpose (GP) transistors, LP transistors benefit from
a smaller leakage current and a higher supply voltage (1.2V).
They unfortunately have a lower tranconductance [4].
There are several benefits from this scaling technology.
In addition to the evident reduction of silicon area, technical
performances are improved. Indeed, the reduction of the gate
resistance increases the gain and the power added efficiency
(PAE).
III. S
IMULATION METHODOLOGY
The principal reason of using this technology is the high
f
max
and its capability to operate at 60GHz. At this frequency,
we have to take into account some other considerations,
principally the electromagnetic effects, responsible for the
degradation of performances. Therefore, small and large
analyses were done to characterize the circuit, especially the
post layout simulation.
A. Transistor Layout Caracterisation
The size of the transistor depends on the maximum
power defined by the user. In our case, it was estimated to
10 dBm. We must not forget that the relationship between
these two parameters is not linear. In fact, losses and the
complexity of modeling increase with the size of the
transistor. This is mainly due to capacitive and inductive
effects of routed elements and silicon substrate loss. The

other important point is the electro-migration phenomenon
and the ageing of components. The nanometer transistors
have a low gate oxide thickness and therefore a low
breakdown and supply voltage. Thus, we must have a strong
current to provide the power. At high frequencies, the
effective lines’ width remains small and hence, insufficient
to sustain a high current due to the skin depth. An
architecture using a parallel amplification topology is
better [8]. We need to know the maximum power delivered
with a single amplification. In other terms, what is the
maximum size of transistor needed to have a good trade-off
between the size and the losses?
Once we have estimated the size of the transistor, it was
important to optimize these three following parameters:
Finger length (w): it directly affects not only the
gate series resistance responsible for the
degradation of gain, but also f
max
(1), which is
proportional to f
t
:
g
ds
t
R
R
ff
2
1
max
= (1)
where
gs
m
t
C
g
f
=
π
2
Number of fingers per transistor (N
f
): it decreases
the total gate resistance which is favorable for f
max
,
but this can induce the system instability.
Number of parallel transistors (N
c
): Obviously, The
system provides more power when we increase N
c
.
However both output impedance and optimal load
(R
opt
) of the transistors drop. The impedance
transformation ratio (r) which is proportional to
power losses caused by the mismatch network,
defined in (3), increases.
opt
L
R
R
r
)50(
=
(2)
We have fixed the size of the driver transistors to 100μm
with (N
f1
, N
c1
) = (100, 1) and for the output stage a size
200μm with (N
f2
, N
c2
) = (100, 1). The routing of the
transistor is based on reducing gate-drain capacitance C
gd
in
order to minimize the S
12
, and thus maximize f
t
, f
max
, and
S
21
. To have signals coming from all transistors’ fingers, in
phase, an equal distance access to the transistors’ pins was
respected.
B. Transistor simulation
As shown in Fig.1, an effort of modeling was necessary
to carry out the small and large signal analysis.
Small signal:
to perform this analysis, a
microwave approach was necessary. Accesses
to gate, drain, and source were simulated with
Ansoft HFSS electromagnetic simulator and
represented by S-parameters blocks. The
overall system illustrated in Fig. 1(a) was
simulated in Cadence environment. This took
into account the effects of distributed elements
and the influence of the ground return path.
Fig. 1: Transistor modeling.
Large signal:
the S-parameters do not have
significance in a non linear regime. A model
with lumped elements is needed [9] and will be
compared to the S-parameters mentioned
above. Routing with high level metals induce
inductive effects and signal delay represented
by L
g,
L
d,
L
s
. On the other hand, high currents
run through the PA requiring the use of wide
lines. This generates non neglected capacitive
effects modeled by C
gd
, C
ds
, and C
gs
.
These reactances are important enough to
change the impedance localization in Smith-
chart and to cause substrate losses.
Conductor losses are modeled by the intrinsic
resistances of accesses; R
g
, R
d
, R
s
. Fig. 1(b)
shows all extracted element.
IV. C
IRCUIT DESIGN
The 60GHz PA shown in Fig. 2 is a single-ended two
stages common source structure. The output transistor is
biased at the optimum linearity current density [10] of
(70mA/200μm) whereas the driver favors the PA gain. Both
two stages are supplied with 0.9V on the drain and 1V on the
gates.
The first stage is biased by a tee polarization (LT, CT)
outside the chip. The second transistor is biased with a
current mirror.
To avoid the series resonance and to have a good quality
factor around 60 GHz. We use 60pH and 72pH inductors.
For capacitances values less than 45fF, MoM capacitors are
used for mismatch, otherwise MIM capacitors are suitable
for both decoupling and mismatch.

(2*100)μ
100μ
VDD1=0.9V
VDD2=0.9V
Vg2=1V
Vg1=1V
L1
L5
L2 L3
L4
CT
IT
I1
Id1
Id2
I2
C1
C2
C3
Fig.2: Schematic of the 60GHz fully integrated 65nm CMOS PA.
We have to control the characteristic impedance of the
transmission lines employed for inter-elements routing.
These lines measure up to λ/20 and can change the
impedance. This change will be all the more significant as
the characteristic impedance is high. It explains the choice of
microstrip lines that are represented by L1, L2, L3, L4, and
L5. In addition to this; Thin-film microstrips (TFMS) have
the advantage of the ground plan shielding that isolates the
conductive substrate. The disadvantage is that the line-width
of TFMS is the unique degree of freedom, to control the
characteristic impedance, once the process parameters are
fixed.
Microstrip lines offer low characteristic impedance and
hence consume a compact area of silicon. The chip size is
0.48*0.6mm² including pads as shown in Fig.3. The input
and output matching impedance of the integrated PA are set
to 50.
Fig.3: Layout of the integrated PA.
V.
SIMULATED RESULTS
Fig.4 presents the PA scattering parameters from the EM
simulation and from the equivalent developed lumped
model. The PA was designed to operate from 57 to 64 GHz
frequency range. The return loss (S
11
) of the PA is less than
-10dB in all the bandwidth. It reaches -22dB at 60GHz. The
simulation shows a maximum small signal gain (S
21
) of
7.6dB.
Thanks to load pull simulations the output was matched
at the optimal load (R
opt
= 10 ) in order to deliver a
maximum power at 60GHz. Stability criteria, isolation
results are reported in table [1].
Fig.4: Simulated S parameters.
Large signal simulations, at 60GHz, were performed in
Cadence environment. Fig5 shows the power transfer
characteristic. Thanks to the high bias current, the PA has a
good OCP1 of 8.9dBm and a saturation power of 13dB.
Fig.6 shows a maximum PAE (3) of 11% in the compression
region.

21 stagestage
PdcPdc
PinPout
PAE
+
=
(3)
Fig.5: Output power versus available input power.
Fig. 6: Power added efficiency and amplifier gain versus input power.
references
This
work
(simulated)
[1] [10] [4]
Technology
(nm)
65 90 90 130
Gain
(dB)
8 9.8 5.2 12
Psat
(dBm)
13 - 9.3 -
PAE
(%)
11 20 7 -
OCP1
(dBm)
8.92 6.7 6.4 2
Consumption
(mA@V)
72@0.9 14@1 28@1.5 36@1.6
(S
11
,S
12
)
(dB, dB)
(-22,-25) (-13,-) (-10,-30) (-20,-)
Table. 1 Performance comparison of different 60GHz CMOS power
amplifiers.
VI. CONCLUSION
In this paper, a 65nm CMOS, 60GHz fully integrated
power amplifier was designed and sent to
STMicroelectronics foundry. It is composed of two common
source stages. To perform small and large signal analysis, a
microwave and system approaches were necessary.
The power amplifier was optimized to ensure a linear
operation for powers up to 10mW it has an OCP1 of 8.9dB
and a maximum power added efficiency of 11% with a gain
of 8dB. These results can be improved by adding a third
stage or using parallel amplification structure.
A
CKNOWLEDGMENT
The authors would like to acknowledge the fabrication
support provided by STMicroelectronics and the LAAS,
Toulouse laboratory for its useful technical information on
the needle probe measurement.
R
EFERENCES
[1] B. Heydari, M. Bohsali,A. Abadi and A. M. Niknejad, “A 60GHz
Power Amplifier in 90nm CMOS Technology”, ISSCC Digest of
Tech. Paper, 2007,pp.769-772.
[2] C.H.Doan, S. Emami, A.M. Niknejad, and R. W Brodersen, “A
60GHz down-converting CMOS single-Gate Mixer,” RFIC Digest of
Tech. Papers, pp. 163-166, June. 2005.
[3] C.H.Doan, S. Emami, A.M. Niknejad, and R. W Brodersen, “Design
of CMOS for 60GHz application,” ISSCC Digest of Technical
Papers, 2004, pp. 440-538.
[4] C.H.Doan, S. Emami,D. Sobel, A.M. Niknejad, and R. W Brodersen,
“A 60GHz CMOS Radio for Gb/s Wireless LAN,” RFIC Digest of
Papers, pp. 225-228, June 2004.
[5] U.Pfeiffer, J. Grryb, D. Liu, B. Gaucher, T. Beukema, B. Floyd, and
S.Reynolds, “A 60GHz Radio Chipset Fully-integrated in a Low-cost
Packaging Technology”, Proceeding of ECTC, pp. 1343-1346, June
2006.
[6] K. Ohata, K. Mauhashi, M. Ito, S. Kishimoto, K. Ikuina, T.
Hashiguchi, N. Takahashi, S.Iwanaga, “ Wireless 1.25GB/s
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[7] F. Gianesello, D.Gloria, S. Montusclat, C. Raynaud, S. Boret, C.
Clement, G. Dambrine, S. Lepilliet, F. Saguin, P.Scheer, Ph. Benech,
J. M. Fournier,”65nm RFCMOS technologies with bulk and HG SOI
substrate wave passives and circuits characterized up to 220 GHZ”,
MTT Microwave Symposium, 2006, pp. 1927-1930.
[8] P. Reymnaert, M. S. J. Steyaert, “A 2.45-GHz 0.13μm CMOS PA
With Parallel Amplification”, IEEE journal of Solid State Circuits,
vol, 42, 2007, pp. 551-562.
[9] S. Emami, C. H. Doan, A.M.Niknejad, R. W. Brodersen, “Large-
signal millimeter-wave CMOS modeling with BSIM3”, RFIC Digest
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and LNA in 90-nm CMOS,”RFIC Symposium, pp. 11-13, June 2006.
Citations
More filters
Proceedings ArticleDOI
01 Jun 2014
TL;DR: In this paper, a 60 GHz power amplifier utilizing a novel technique to achieve high efficiency at high output power levels was presented, where the output power of a conventional class A power amplifier was combined with the power provided by an amplifier operating at a different class to achieve higher efficiency at higher output levels.
Abstract: This paper presents a 60 GHz power amplifier utilizing a novel technique to achieve high efficiency at high output power levels. The proposed topology provides the capability of dual mode operation. The output power of a conventional class A power amplifier will be combined with the power provided by an amplifier operating at a different class to achieve higher efficiency at higher output levels. Driver stages to provide high power gain consist of an enhanced cascode stage followed by a common source amplifier with transformer-coupled impedance matching networks. Fabricated in 65 nm CMOS process, the measured gain of the 0.32 mm2 power amplifier is 17.7 dB at 60 GHz with a wide 3dB band width of 12 GHz while consuming 378 mW from a 1.2V supply. A maximum saturated output power of 16.8 dBm is measured with the 14.5% peak power added efficiency at 60 GHz.

13 citations


Cites background or methods from "A 60GHz, 13 dBm fully integrated 65..."

  • ...To date, there have been several CMOS PAs targeting high gain and output power at 60 GHz [2]-[11]....

    [...]

  • ...Therefore, in all reported 60 GHz CMOS PAs, different power combining techniques such as using onchip transformers, Wilkinson power combiners and distributed active transformers (DAT) are proposed to increase the output power of CMOS PAs [2]-[11]....

    [...]

Proceedings ArticleDOI
Sergio Saponara1, L. Mattii1, Bruno Neri1, Federico Baronti1, Luca Fanucci1 
29 Dec 2014
TL;DR: This work presents the design of a 60 GHz OOK transceiver, with on-chip integrated antenna, for multi Gbit short-range wireless communication, selected as target to prove that high-speed fully-integrated RF transceivers can be realized also with low cost digital technologies.
Abstract: This work presents the design of a 60 GHz OOK transceiver, with on-chip integrated antenna, for multi Gbit short-range wireless communication. A 65 nm bulk CMOS technology has been selected as target to prove that high-speed fully-integrated RF transceivers can be realized also with low cost digital technologies, suited for wireless consumer applications. The OOK modulation scheme allows for low complex transceiver architecture with all passive and active devices integrated on-chip. At TX side the power stage combines two class-A power amplifiers in a pseudo differential scheme, each made up of a 2 stage Common Source topology with a GT gain of 6.8 dB and a OP1dB of 8.2 dBm. The whole transmitter allows for an output power of about 11 dBm. The antenna is integrated on-chip adopting an half-wavelength dipole topology. Simulated results are a radiation efficiency of 38% and a gain of -1.76 dBi. At RX side a single-stage cascode LNA with a GT gain of 11.46 dB and a noise figure (NF) of 4.69 dB is followed by an OOK demodulator realized with a simple envelope detector. Since both antenna and LNA are integrated on-chip, the impedance matching is not constrained to a 50 Ω value, but its value can be tuned to find an optimal trade-off between NF and gain of the receiver. Combining the proposed RF transceiver with the use of Reed-Solomon channel coding in the digital baseband a data link with an effective data rate of 2 Gb/s can be implemented; the BER is less than 10-5 and 10-12 at 2 m and 1.1 m distance respectively.1

8 citations

Proceedings ArticleDOI
11 Nov 2013
TL;DR: This paper presents a compact 60 GHz power amplifier utilizing a novel 4-way multi-conductor power combiner and splitter with the advantage of lower insertion loss and higher efficiency compared to the conventional distributed active transformer topology.
Abstract: This paper presents a compact 60 GHz power amplifier utilizing a novel 4-way multi-conductor power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area of 0.025 mm2 with the advantage of lower insertion loss and higher efficiency compared to the conventional distributed active transformer topology. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65 nm CMOS process, the measured gain of the 0.19 mm2 power amplifier is 18.8 dB at 60 GHz with 3dB band width of 4 GHz while consuming 424 mW from a 1.4V supply. A maximum saturated output power of 18.3dBm is measured with the 15.9% peak power added efficiency at 60 GHz.

6 citations


Cites background or methods from "A 60GHz, 13 dBm fully integrated 65..."

  • ...To date, there have been several CMOS PAs targeting high gain and output power at 60 GHz [2]-[11]....

    [...]

  • ...Therefore, in all reported 60 GHz CMOS PAs, different power combining techniques such as using transformers, Wilkinson power combiners and distributed active transformers (DAT) are proposed to increase the output power of CMOS PAs [2]-[11]....

    [...]

Proceedings ArticleDOI
31 Dec 2012
TL;DR: A fully integrated power amplifier working at 60GHz band and implemented in CMOS 65nm technology is described, using the ring topology of a distributed active transformer (DAT) to realize efficient power combination and impedance transformation simultaneously.
Abstract: This paper describes a fully integrated power amplifier working at 60GHz band and implemented in CMOS 65nm technology. The ring topology of a distributed active transformer (DAT) is applied to realize efficient power combination and impedance transformation simultaneously. The design consists of the transformer, active stages, and input power divider, and the matching networks between the components are implemented to form the complete system. The power amplifier achieves a simulated 21.36 dBm output power at 1 dB compression, with 1dB bandwidth of 12.5 GHz. The power added efficiency of total system is 4.56% and the transducer gain is 4.95 dB.

4 citations

Proceedings ArticleDOI
01 Oct 2012
TL;DR: In this paper, a cylindrical dielectric resonator antenna is micromachined as a part of the package surrounding other active elements and magnetically coupled to a nearby integrated coplanar-fed slotted dipole.
Abstract: In this paper, a completely packaged solution is presented for high data rate radio front end operating around 60 GHz. A cylindrical dielectric resonator antenna is micromachined as a part of the package surrounding other active elements. This resonator is magnetically coupled to a nearby integrated coplanar-fed slotted dipole. Simulation results show a 6.1GHz impedance matching bandwidth (VSWR=2) with a gain greater than 5dBi throughout the entire bandwidth.

4 citations

References
More filters
Proceedings ArticleDOI
13 Sep 2004
TL;DR: In this paper, the viability of digital CMOS as a future mm-wave technology, capable of exploiting the 60GHz band, is explored, and the optimal device design and appropriate mmwave models are presented, from modeling of transistors in 0.13/spl mu/m technology.
Abstract: The viability of digital CMOS as a future mm-wave technology, capable of exploiting the 60GHz band, is explored. Optimal device design and appropriate mm-wave models are presented. From modeling of transistors in 0.13/spl mu/m technology a three cascode-stage amplifier at 1.5 volts would provide 11 dB of gain at 60GHz using 54mW.

134 citations


"A 60GHz, 13 dBm fully integrated 65..." refers methods in this paper

  • ...In the ISM band, a 7GHz unlicensed bandwidth around 60GHz is employed [1] [2] [3] [4]....

    [...]

Proceedings ArticleDOI
T. Yao1, M. Gordon1, K.H.K. Yau1, M.T. Yang2, Sorin P. Voinigescu1 
11 Jun 2006
TL;DR: In this article, a 90-nm RF-CMOS process with a 9-metal layer copper backend and transistor f/sub T/f/sub max/ of 140GHz/170GHz is reported.
Abstract: 60-GHz power (PA) and low-noise (LNA) amplifiers implemented in a 90-nm RF-CMOS process with thick 9-metal layer copper backend and transistor f/sub T//f/sub max/ of 140GHz/170GHz are reported. The PA operates from a 1.5V supply with 5.2dB power gain, a 3-dB bandwidth >13GHz, a P/sub 1dB/of +6.4dBm with 7% PAE and a saturated output power of +9.3dBm at 60GHz. The LNA features 14.6dB gain, an IIP3 of -6.8dBm, and a simulated NF of 4.5dB, while drawing 16mA from a 1.5V supply. Both circuits employ inductors which reduce the total PA and LNA die sizes to 0.35 /spl times/ 0.43 mm/sup 2/ and 0.35 /spl times/ 0.40 mm/sup 2/, respectively.

100 citations


"A 60GHz, 13 dBm fully integrated 65..." refers background in this paper

  • ...references This work (simulated) [1] [ 10 ] [4]...

    [...]

  • ...The output transistor is biased at the optimum linearity current density [ 10 ] of (70mA/200μm) whereas the driver favors the PA gain....

    [...]

Proceedings ArticleDOI
12 Jun 2005
TL;DR: In this paper, a quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60 GHz, is presented and a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers.
Abstract: A quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60-GHz, is presented. Also a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers. The performance of a fully-integrated mixer fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency (RF) of 60 GHz, intermediate frequency (IF) of 2 GHz, and low LO power of 0 dBm, conversion loss is better than 2 dB, and an input-referred 1-dB compression point of -3.5 dBm was measured.

87 citations


"A 60GHz, 13 dBm fully integrated 65..." refers methods in this paper

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    [...]

Journal ArticleDOI
TL;DR: A fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented, where four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure to have a lower power loss.
Abstract: In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced.

83 citations


"A 60GHz, 13 dBm fully integrated 65..." refers methods in this paper

  • ...An architecture using a parallel amplification topology is better [ 8 ]....

    [...]

Proceedings ArticleDOI
06 Jun 2004
TL;DR: In this article, the effect of parasitics on the high-frequency operation of CMOS transistors is discussed, and a standard intrinsic BSIM3v3 model card is augmented with lumped elements to model these effects.
Abstract: A large-signal modeling methodology based upon a modified BSIM3v3 transistor model is presented which targets MM-wave CMOS applications. The effect of parasitics on the high-frequency operation of CMOS transistors is discussed, and a standard intrinsic BSIM3v3 model card is augmented with lumped elements to model these effects. Core BSIM parameters are extracted to match the measured DC I-V curves of a fabricated common-source NMOS transistor. Measured S-parameters are used to extract external parasitic component values to obtain a bias-dependent small-signal MM-wave frequency fit up to 65 GHz. The large-signal MM-wave accuracy of the model is verified by measuring the output harmonics power under large-signal excitation. Comparisons of measurements with the simulations show good agreement up to 60 GHz.

44 citations


"A 60GHz, 13 dBm fully integrated 65..." refers methods in this paper

  • ...A model with lumped elements is needed [9] and will be compared to the Sparameters mentioned above....

    [...]

Frequently Asked Questions (1)
Q1. What are the contributions mentioned in the paper "A 60ghz, 13dbm fully integrated 65nm rf-cmos power amplifier" ?

A 65nm CMOS, 60GHz fully integrated power amplifier ( PA ) from STMicroelectronics has been designed for low cost Wireless Personal Area Network ( WPAN ) this paper.