A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration
15 Oct 2012-pp 1-4
TL;DR: A 5Gbps bi-directional RF-Interconnect with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS and supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter.
Abstract: A 5Gbps bi-directional RF-Interconnect (RF-I) with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS. The baseband data are modulated in RF-I by using a 60GHz carrier in ASK format. An on-chip differential transmission line (TL) is used as the communication channel, which minimizes the latency (9ps/mm) only under the speed-of-light limitation. We insert λ/4 directional couplers for implementing multi-drops without signal reflection. We also use MOS switches along the signal path to reconfigure/arbitrate communication priority for multi-drops. This design consists of four TX/RX drops along a 5.5mm TL ring, supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter. The tested data rate of the RF-I is 5Gbps with lower than 10−12 BER. The average power consumptions for the link are 1.33pJ/b and 0.24pJ/b/mm.
Citations
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TL;DR: In this paper, a 60 GHz on-off keying (OOK) transmitter for wireless network-on-chip (WiNoC) applications is presented, which consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator.
Abstract: This paper presents a high-efficiency 60-GHz on-off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip commu- nication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is de- rived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation tech- nique, resulting in a 30-dB on-off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of 0.077 mm . A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit. Index Terms—Bulk driven, CMOS, drive amplifier (DA), low power, millimeter wave, modulator, neutralization, on-off keying (OOK), transmitter (TX), voltage-controlled oscillator (VCO), wireless network-on-chip (WiNoC).
77 citations
TL;DR: This paper presents for the first time the design, fabrication, and demonstration of a micromachined silicon dielectric waveguide based sub-THz interconnect channel for a high-efficiency, low-cost sub-HZ interconnect, aiming to solve the long-standing intrachip/interchip interconnect problem.
Abstract: This paper presents for the first time the design, fabrication, and demonstration of a micromachined silicon dielectric waveguide based sub-THz interconnect channel for a high-efficiency, low-cost sub-THz interconnect, aiming to solve the long-standing intrachip/interchip interconnect problem. Careful studies of the loss mechanisms in the proposed sub-THz interconnect channel are carried out to optimize the design. Both theoretical and experimental results are provided with good agreement. To guide the channel design, a new figure of merit is also defined. The insertion loss of this first prototype with a 6-mm-long interconnect channel is about 8.4 dB at 209.7 GHz, with a 3-dB bandwidth of 12.6 GHz.
46 citations
Cites background from "A 60GHz on-chip RF-Interconnect wit..."
...Digital Object Identifier 10.1109/TMTT.2015.2504443 Interconnect research has been active in two areas: optical interconnect [3]–[6] and electrical interconnect [7]–[11]....
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...Chang's group [11] demonstrates a design on wired interconnect based on-chip transmission line, which also faces the challenge of increasingly high losses versus frequencies....
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TL;DR: In this paper, the authors proposed a 0.1-1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high energy efficiency and low-crosstalk interconnect.
Abstract: Traditional TEM-based I/O communication through either PCB traces or free space has significant path loss and electromagnetic (EM) interferences that are hardly employed toward low-power and dense I/Os for data server. We propose a 0.1–1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high-energy efficiency and low-crosstalk interconnect. The surface wave can be established with on-chip generation and further deployed for signal propagation by corrugating periodical grooves onto the traditional transmission line. It will result in a strongly localized electromagnetically wave onto the surface of top-layer metal in wideband, leading to the broadband low EM coupling between many core and memories. Moreover, we have also developed a high on/off ratio split-ring-resonator-based modulator to support the sub-THz I/O communication. The proposed SPP interconnect achieves data rate of 25 Gb/s with 0.016 pJ/b/mm energy efficiency at 140 GHz in 65-nm CMOS. In addition, two surface-wave channels placed with 2.4- $\mu \text{m}$ spacing exhibits an average −28-dB crosstalk ratio.
38 citations
Cites background or methods from "A 60GHz on-chip RF-Interconnect wit..."
...The proposed SPP-wave interconnect is compared to conventional BB signaling [3], [6], [7], optical-I [1], [23], and RF-I [2], [5]....
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...With the use of passive modulator, the proposed interconnect consumes only 8-mW power, which is less than RF-I using active modulator reported in [2] and [5]....
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...The on-chip modulator can be conventionally implemented based on inductive devices loaded with active MOS transistors [5], [19], [20]....
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...Though multichannel RF interconnects have been introduced for higher aggregate data bandwidth (BW) [2], [5], the CMOS back end of line (BEOL) is normally thin, leading to a high loss and also remarkable EM crosstalk....
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TL;DR: In this paper, a dielectric waveguide (DWG)-based ortho-mode sub-THz interconnect channel for planar chip-to-chip communications is presented.
Abstract: This paper presents for the first time the design, fabrication, and demonstration of a dielectric waveguide (DWG)-based ortho-mode sub-THz interconnect channel for planar chip-to-chip communications. By combining the proposed new transition of microstrip line with DWG orthogonally, the ortho-mode transition is constructed to form an ortho-mode channel. The measured minimum insertion losses for the $E_{y11}$ mode and the $E_{x11}$ mode are 6.6 dB with 20.3-GHz 3-dB bandwidth and 6.5 dB with 55.2-GHz 3-dB bandwidth, respectively. The simulation and measurement results agree well with each other.
36 citations
TL;DR: In this article, a novel dielectric waveguide based G-band interconnect is presented, which uses a new transition of microstrip line to dielectrics waveguide and achieves low insertion loss and wide bandwidth.
Abstract: This paper presents a novel dielectric waveguide based G-band interconnect. By using a new transition of microstrip line to dielectric waveguide, the interconnect achieves low insertion loss and wide bandwidth. The measured minimum insertion loss is 4.9 dB with 9.7 GHz 1-dB bandwidth. Besides, the structure is based on standard micromachined processing and easy to integrate with conventional packaging.
33 citations
Cites background from "A 60GHz on-chip RF-Interconnect wit..."
...FUELED by the demand of high data rate and low loss chip-to-chip communication, the interconnect gap have been a challenging issue over decades [1], [2]....
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References
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20 Jun 2009
TL;DR: Firefly is a hybrid, hierarchical network architecture that consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using nanophotonics - exploiting the benefits of electrical signaling for short, local communication while nanophotinics is used only for global communication to realize an efficient on-chip network.
Abstract: Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the increasing number of cores. Recent advances in silicon nanophotonics create new opportunities for on-chip networks. To efficiently exploit the benefits of nanophotonics, we propose Firefly - a hybrid, hierarchical network architecture. Firefly consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using nanophotonics - exploiting the benefits of electrical signaling for short, local communication while nanophotonics is used only for global communication to realize an efficient on-chip network. Crossbar architecture is used for inter-cluster communication. However, to avoid global arbitration, the crossbar is partitioned into multiple, logical crossbars and their arbitration is localized. Our evaluations show that Firefly improves the performance by up to 57% compared to an all-electrical concentrated mesh (CMESH) topology on adversarial traffic patterns and up to 54% compared to an all-optical crossbar (OP XBAR) on traffic patterns with locality. If the energy-delay-product is compared, Firefly improves the efficiency of the on-chip network by up to 51% and 38% compared to CMESH and OP XBAR, respectively.
411 citations
"A 60GHz on-chip RF-Interconnect wit..." refers background in this paper
...With transmission-gatebased switches, signal on the main channel can be terminated to Z0 (100Ω differentially) or passed to subsequent drops [2][4]....
[...]
...Therefore, the next generation of NoC architecture demands the benefit of having on-chip high-speed interconnect with multi-drop and arbitration capabilities as data buses [2][4]....
[...]
...Previously published multi-drop works are either too powerhungry (optical link involves power-consuming O/E and E/O conversions) [4], or has long latency and lacks arbitration capability because of reflections introduced by multiple drops at the baseband and unpredictable receiving priorities [5]....
[...]
24 Oct 2008
TL;DR: This paper explores the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology, and investigates the costs associated with this technology, and examines the latency and bandwidth benefits that it can provide.
Abstract: In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.
276 citations
"A 60GHz on-chip RF-Interconnect wit..." refers background in this paper
...RF modulated and transmission-line-based interconnects (RF-I) have been demonstrated as superior in latency, scalability, re-configurability, bandwidth and power efficiency [1]-[3]....
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TL;DR: This paper presents a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate.
Abstract: Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.
83 citations
08 Nov 2008
TL;DR: A novel interconnect design exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture is proposed, and it is found that the adaptiveRF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65% including the overhead incurred for supporting RF- I.
Abstract: As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of radio frequency interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural and efficient support for multicast. In this paper, we propose a novel interconnect design, exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture. We find that our adaptive RF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65% including the overhead incurred for supporting RF-I.
70 citations
"A 60GHz on-chip RF-Interconnect wit..." refers background in this paper
...According to [2], RF-I global links combined with local RC wires provide the inter-core network with either 1....
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...With transmission-gatebased switches, signal on the main channel can be terminated to Z0 (100Ω differentially) or passed to subsequent drops [2][4]....
[...]
...This architecture brings superior flexibility and scalability, which potentially saves considerable bandwidth, latency and power on the NoC interconnects [2]....
[...]
...Therefore, the next generation of NoC architecture demands the benefit of having on-chip high-speed interconnect with multi-drop and arbitration capabilities as data buses [2][4]....
[...]
TL;DR: A novel transceiver that consists of a single differential-amplifier and serves as both a transmitter and a receiver for transmitting signals to multipoint for on-chip high-speed networks that have big impact in chip performances is proposed.
Abstract: This paper investigates a bidirectional- and multi-drop-transmission-line interconnect for on-chip high-speed networks that have big impact in chip performances. Point-to-point on-chip transmission line interconnects have been developed and demonstrated widely. The present paper applies transmission line interconnect technologies to multipoint-to-multipoint on-chip communications. We propose the novel transceiver that consists of a single differential-amplifier and serves as both a transmitter (Tx) and a receiver (Rx) for transmitting signals to multipoint. The 5-mm-long prototype interconnect with six transceivers performs 8 Gbps signaling with power dissipation of 1.2 mW per transceiver in a 90 nm Si CMOS process. Our interconnect achieves multipoint communications with small delay and high power efficiencies.
65 citations
"A 60GHz on-chip RF-Interconnect wit..." refers background in this paper
...Previously published multi-drop works are either too powerhungry (optical link involves power-consuming O/E and E/O conversions) [4], or has long latency and lacks arbitration capability because of reflections introduced by multiple drops at the baseband and unpredictable receiving priorities [5]....
[...]