A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator
01 Feb 2008-pp 246-610
TL;DR: This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR because it uses a comparator, named time-domainComparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
Abstract: The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
Citations
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TL;DR: The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator and the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity.
Abstract: A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.
587 citations
Cites background from "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..."
...The power dissipation is just derived from what is needed to drive the bottom-plate parasitic of the capacitive arrays, while in the conventional charge-redistribution [13], [22] and the charge-recycling [14] methods the necessary MSB “up” transition costs significant switching energy and settling time....
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TL;DR: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller.
Abstract: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.
377 citations
18 Mar 2010
TL;DR: This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT delay variation.
Abstract: Rapid growth in the demand for “Green-IT” or medical applications requires power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The ADC is integrated in 65nm CMOS and achieved 10b at 50MS/s while consuming 820µW from a 1.0V supply.
174 citations
Cites background from "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..."
...Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]....
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TL;DR: Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure- of-merit (FoM) without any calibration.
Abstract: In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.
147 citations
Cites background from "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..."
...The start signal is assumed to be periodic which is the case for TDCs used in ADPLLs, ADDLLs and time-domain ADCs....
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...Recently however, TDCs have become increasingly more important with the advent of digital-friendly analog and mixed-signal circuits such as all-digital PLL/DLLs [5]–[11] and time-domain ADCs [12]–[18]....
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...In ADCs, figure of merit (FoM) is well defined as the following equation: (1) where effective number of bits (ENOB) is measured by dynamic testing....
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TL;DR: Detailed analysis proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages by effectively eliminating static power consumption in the proposed time-domain comparator.
Abstract: This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.
141 citations
Cites background or methods from "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..."
...For the binary phase detector (PD), a flip-flop can be conventionally used [16] as it is the simplest and fastest circuit....
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...sion in [16], however, is not suitable for low-voltage operation and is sensitive to setup/hold uncertainties of D-F/F....
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...As an alternative to the conventional voltage-mode comparator, the time-domain comparator was recently proposed in [16]....
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References
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TL;DR: The design and implementation of an ADC to meet the unique requirements of sensor networks is described and the ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW, one of the lowest ever reported.
Abstract: A low-energy successive approximation analog-to-digital converter (ADC) targeted for use in distributed sensor networks is presented The individual nodes combine sensing, computation, communications, and power into a tiny volume Energy is extremely limited, forcing the nodes to operate with very low duty cycles This paper describes the design and implementation of an ADC to meet the unique requirements of sensor networks The ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW This energy consumption is one of the lowest ever reported
305 citations
"A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..." refers methods in this paper
...To achieve this target, the successive approximation algorithm is a convenient solution, because it requires only a comparator, a capacitive array and digital logic [1, 2]....
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Proceedings Article•
01 Dec 200644 citations
18 Sep 2006
TL;DR: Efficiency of the comparator is increased by an offset compensating latch, while noise performance and common-mode rejection are improved by a modified capacitor network.
Abstract: A 0.18mum CMOS 12b 100kS/s successive approximation ADC is presented. The entire ADC consumes 25muW from a 1V supply and achieves an SNDR of 65dB. Its sampling rate can be scaled, yielding linear power savings. Efficiency of the comparator is increased by an offset compensating latch, while noise performance and common-mode rejection are improved by a modified capacitor network
42 citations
"A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..." refers methods in this paper
...To achieve this target, the successive approximation algorithm is a convenient solution, because it requires only a comparator, a capacitive array and digital logic [1, 2]....
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15 Nov 2004
TL;DR: A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage with new low power design solutions in the ADC comparator and the built-in reference buffer.
Abstract: A CMOS 1 MSps 10 bit charge-redistribution SAR ADC processes single-ended signals with 1 LSB accuracy selectable input ranges up to supply voltage A new DAC architecture presents the benefits of a differential approach while sampling single-ended signals Thanks to new low power design solutions in the ADC comparator and the built-in reference buffer, the total ADC power consumption is only 27 mW at 24 V supply and 1 MSps The active area is 04 mm/sup 2/ in a 035 /spl mu/m CMOS process
37 citations
"A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC..." refers background in this paper
...Moreover, the value of the scaling capacitance between the two arrays is one instead of being fractional [3]....
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