A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback
21 Oct 2019-Vol. 2, Iss: 9, pp 87-90
TL;DR: This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp.
Abstract: This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback. Due to the resetting environment of the incremental operation, the FIR digital-to-analog converter comes with added challenges to design. Thus, a differential resetting scheme between adjacent FIR taps is introduced, which allows the use of a sufficiently large number of taps in the incremental operation, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp. A prototype is fabricated in a 180-nm CMOS process, occupying an active area of 0.175 mm2. The prototype achieves a peak SNR/SNDR of 86/83 dB, a dynamic range (DR) of 91.5 dB, and a peak spurious-free DR of 94.3 dB at a conversion rate of 200 kS/s. The power consumption is 1.27 mW from a 3-V power supply. This results in a Schreier FoM of 170.4 dB.
Citations
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TL;DR: Various design techniques for improving the energy-efficiency of the IADCs are described and intended to serve as a starting point for the development of a new energy-efficient IADC.
Abstract: In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.
33 citations
TL;DR: This long review paper summarizes and discusses recent trending IC design directions and challenges, and tries to give the readers big/cool pictures on each selected small/hot topics.
Abstract: For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.
14 citations
TL;DR: In this paper, the effects of FIR feedback on the maximum stable amplitude of an incremental delta-sigma data converter are examined. But, the effect of FIR is limited in terms of the modulator's linearity and the quantizer's complexity.
Abstract: Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator’s linearity, reducing the quantizer’s complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory.
5 citations
12 Oct 2020
TL;DR: This paper describes the challenges that come with acquiring an FIR DAC in an incremental ΔΣ modulator and two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator.
Abstract: Recent state-of-the-art designs have shown that high jitter robustness and low integrator dynamics, thus better linearity can be achieved in a single-bit continuous-time (CT) delta-sigma (ΔΣ) modulator by adapting a finite impulse response (FIR) filter in the feedback digital-to-analog converter (DAC). However, when applying this to CT incremental ΔΣ modulators, after each periodic reset of the loop-filter, the output of each FIR tap is unrelated to the input signal and a certain amount of time is needed to settle back to a normal operation. This results in a severe swing overshoots at the output of the integrators in the initial phase of every incremental ΔΣ conversion cycle, which limits the dynamic range (DR) of the modulator and thus counteracts the benefits of the FIR DAC. This paper describes the challenges that come with acquiring an FIR DAC in an incremental ΔΣ modulator. Additionally, two design techniques are shown to mitigate the swing overshoots and achieve a normal operation of the modulator. This allows higher number of FIR taps to be used in an incremental ΔΣ modulator, which is very beneficial to promote high speed/resolution designs.
5 citations
TL;DR: In this article, a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation is presented.
Abstract: This work describes a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation to achieve high resolution data conversion. The circuits in the first step is acting as a first-order incremental analog-to-digital converter (IADC). Finite impulse response (FIR) DAC is incorporated in the loop filter to reduce the transient voltage step. It is reconfigured as a 2-C SAR to perform extended counting technique in the second step. Only one opamp is re-used in both steps. The hardware is prototyped in $0.18~\mu \text{m}$ CMOS technology, and the hybrid ADC accomplishes a measured DR / SNR / SNDR of 100.2 / 97.1 / 96.6 dB and an input signal bandwidth of 1.2 kHz. Operated at 1.5-V, it consumes $33.2~\mu \text{W}$ , and this achieves a Walden figure-of-merit (FoM) of 0.25 pJ/conversion-step and Schreier FoM of 175.8 dB.
5 citations
References
More filters
TL;DR: In this paper, a /spl Delta/spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described, which is effective even for very low oversampling ratios, and can be used for any modulation order.
Abstract: A /spl Delta//spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described. The technique is effective even for very low oversampling ratios, and can be used for any modulation order. Techniques for reducing other nonideal effects are also proposed.
575 citations
"A 94.3-dB SFDR, 91.5-dB DR, and 200..." refers background in this paper
...(CIFF) architecture, including a low-distortion direct input path to the summing node before the quantizer [7] has been chosen....
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TL;DR: This work gives a method for stabilizing a single-bit continuous-time delta-sigma modulator that uses an FIR feedback DAC and shows that increasing the number of taps beyond a certain number does not improve performance.
Abstract: Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.
104 citations
"A 94.3-dB SFDR, 91.5-dB DR, and 200..." refers background or methods in this paper
...In addition, the element mismatch between the FIR taps alters only the frequency response of the FIR transfer function and does not result in any harmonic distortion, which is very advantageous [8]....
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...A two stage feed-forward compensated architecture is chosen for the design of the three amplifiers within the CT loop filter [8]....
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...The state-ofthe-art of free-running modulators has shown that FIR DACs are very beneficial for single-bit operation [8]....
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...The intention of the FIR DAC is to significantly reduce the high-frequency quantization noise and to smoothen the feedback signal of the outermost DAC F(z) [8]....
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TL;DR: This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems that can achieve high-resolution without sacrificing the conversion rate by using two continuous-time incremental sigma-delta ADCs in a pipeline configuration.
Abstract: This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 $\mu{\rm m}$ CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 $\mu{\rm W}$ , which corresponds to a figure-of-merit of 0.85 pJ/conv.
71 citations
"A 94.3-dB SFDR, 91.5-dB DR, and 200..." refers background in this paper
...Digital Object Identifier 10.1109/LSSC.2019.2930172 An alternative is the implementation of a continuous-time (CT) I- modulator featuring the known advantages of free-running CT modulators, such as resistive input impedance, relaxed dynamic requirements of the opamps, as well as a signal transfer function (STF) presenting some implicit AAF [4], [5]....
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...Even though the sampling capacitor shrinks and the anti-aliasing filter (AAF) implementation relaxes by oversampling, the drawback of the SC driver remains as it has to operate at higher sampling frequency fs. Manuscript received June 3, 2019; revised July 12, 2019; accepted July 17, 2019....
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...Though, state-of-the-art CT I- modulators feature only small bandwidths and low robustness to clock jitter [4], [6]....
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...Even though CT I- modulators are true Nyquist-rate converters, i.e., each output value is a direct digital estimate of the corresponding input value, CT I- modulators still feature a CT STF, which can be used to support the AAF [5]....
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...fer function (STF) presenting some implicit AAF [4], [5]....
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TL;DR: An exact design methodology for IDCs is proposed, which optimizes the signal-to-noise ratio of the converter under practical design constraints, and allows the designer to apportion the noise budget in an arbitrary manner between thermal and quantization noise.
Abstract: Incremental data converters (IDCs) are useful in instrumentation and measurement applications, where low-frequency analog signals need to be converted into digital form with high accuracy and low power dissipation. They are particularly well suited for applications where a single analog-digital converter is multiplexed between many channels. This paper proposes an exact design methodology for IDCs, which optimizes the signal-to-noise ratio of the converter under practical design constraints. The process also allows the designer to apportion the noise budget in an arbitrary manner between thermal and quantization noise. The design process is illustrated by an example which describes the optimization of a third-order multiplexed IDC.
40 citations
"A 94.3-dB SFDR, 91.5-dB DR, and 200..." refers background in this paper
...The input resistor Rin is solely sized to fulfill the thermal noise requirements, taking into account the thermal-noise-penalty factor that comes with higher-order I- modulators due to the unequal weights within the digital reconstruction filter [9]....
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01 Feb 2018
TL;DR: This paper presents a 20b 1MS/s SAR ADC with signal-independent background-calibration to address the challenge of one-time factory calibration for precision SAR ADCs.
Abstract: The SAR ADC is the architecture of choice for high-precision Nyquist ADCs (>16b) with MS/s speed. To achieve the required linearity performance, precision SAR ADCs require calibration to correct mismatch errors in the capacitive digital-to-analog converter (CDAC). One-time factory calibration suffers from aging, temperature sensitivity, and package and PCB stress while foreground calibration precludes continuous ADC operation. This paper presents a 20b 1MS/s SAR ADC with signal-independent background-calibration to address this challenge.
38 citations
"A 94.3-dB SFDR, 91.5-dB DR, and 200..." refers methods in this paper
...To achieve high resolution, calibration techniques [1], mismatcherror-shaping, or noise shaping are often used....
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