A bus encoding technique for power and cross-talk minimization
05 Jan 2004-pp 443-448
TL;DR: No Adjacent Transition (NAT) coding scheme is proposed, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk in system-level buses.
Abstract: Considerable research has been done in the area of bus-encoding techniques, for either power minimization or cross-talk elimination in system-level buses, but not both together. We propose No Adjacent Transition (NAT) coding scheme, a bus encoding technique that simultaneously reduces power consumption and eliminates cross-talk. NAT-encoding and decoding algorithms are proposed and an analytical study of power dissipation is presented.
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Book•
01 Jan 2008
TL;DR: This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design, and will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on- chip communication architectures.
Abstract: Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years
224 citations
01 Jan 2014
TL;DR: A novel ω-LAT coding scheme is proposed to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array and combining with the Transition Signaling, the LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosStalk and power consumption.
Abstract: 3D integration is one of the promising solutions to overcome the interconnect bottleneck with vertical interconnect through-silicon vias (TSVs). This paper investigates the crosstalk in 3D IC designs, especially the capacitive crosstalk in TSV interconnects. We propose a novel ω-LAT coding scheme to reduce the capacitive crosstalk and minimize the power consumption overhead in the TSV array. Combining with the Transition Signaling, the LAT coding scheme restricts the number of transitions in every transmission cycle to minimize the crosstalk and power consumption. Compared to other 3D crosstalk minimization coding schemes, the proposed coding can provide the same delay reduction with more affordable overhead. The performance and power analysis show that when ω is 4, the proposed LAT coding scheme can achieve 38% interconnect crosstalk delay reduction compared to the data transmission without coding. By reducing the value of ω, further reduction can be achieved1.
27 citations
Cites methods or result from "A bus encoding technique for power ..."
...Similar to the analysis in [10], the equation of P s k is shown as follows:...
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...Since the LAT code is derived from 2D No Adjacent Transition (NAT) code [10], we briefly review the NAT coding scheme which is used on 2D design and can reduce the bus crosstalk delay....
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...In order to minimize both crosstalk and power, the NAT coding scheme is proposed [10]....
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...Several crosstalk minimization techniques have been proposed in 2D designs, such as active shielding [9], data coding [10]–[12], and wire spacing [13]....
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TL;DR: An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of fibonacci-based binary codeword are utilized to search the proper codewords.
Abstract: Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a $3 \times 3$ TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.
24 citations
TL;DR: A theoretical analysis of BI coding for coupling reduction for uncorrelated uniformly distributed data is conducted and a set of closed-form formulas for computing the number of couplings per bus transfer for a nonpartitioned versus a partitioned bus is found.
Abstract: Bus-invert (BI) coding is the first encoding method for reducing peak and average self-switching power on a bus. It can also reduce capacitive coupling between bus lines. Although it is no longer used as a stand-alone method, it is often used as a starting point for developing a more sophisticated method. Despite its wide use, researchers in the past often resorted to simulations or depended on their intuition to obtain the switching and coupling characteristics. We clearly need a simple but accurate way to carry out this task. We previously published results on BI coding analysis for switching activity reduction. In this paper we conduct a theoretical analysis of BI coding for coupling reduction for uncorrelated uniformly distributed data. Our findings include a set of closed-form formulas for computing the number of couplings per bus transfer for a nonpartitioned versus a partitioned bus. These formulas are simple and easily understandable. They can be readily used for calculating couplings by simply plugging one or two parameter values into them.
19 citations
TL;DR: This paper provides a straightforward architecture of a non-pipelined bit-parallel multiplier using the new formula, which has lower space complexity than and comparable time complexity to previous Mastrovito multipliers' for all irreducible trinomials.
Abstract: Koc and Sunar proposed an architecture of the Mastrovito multiplier for the irreducible trinomial f(x)=xn+xk+1, where k ≠ n/2 to reduce the time complexity. Also, many multipliers based on the Karatsuba-Ofman algorithm (KOA) was proposed that sacrificed time efficiency for low space complexity. In this paper, a new multiplication formula which is a variant of KOA presented. We also provide a straightforward architecture of a non-pipelined bit-parallel multiplier using the new formula. The proposed multiplier has lower space complexity than and comparable time complexity to previous Mastrovito multipliers' for all irreducible trinomials.
17 citations
References
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TL;DR: In this article, the bus-invert method of coding the I/O was proposed to decrease the bus activity and thus decrease the peak power dissipation by 50% and the average power disipation by up to 25%.
Abstract: Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. >
1,011 citations
01 Jan 1995
TL;DR: The bus-invert method of coding the I/O is proposed which lowers the bus activity and thus decreases theI/O peak power dissipation by 50% and the I-O average power Dissipation by up to 25%.
Abstract: Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. >
892 citations
TL;DR: An expression for the coupled noise integral and a bound for the peak coupled noise voltage are derived which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work.
Abstract: The performance of high-speed electronic systems is limited by interconnect-related failure modes such as coupled noise. We propose new techniques for alleviating the problems caused by coupling between signal lines on integrated circuits. We show that models used by previous work on coupled noise-constrained layout synthesis do not allow the use of several important degrees of freedom. These degrees of freedom include the ability to utilize dynamic noise margins rather than static noise margins, the dependence of coupled noise on drive strength, and the possibility of using overlaps to reduce susceptibility to noise. We derive an expression for the coupled noise integral and a bound for the peak coupled noise voltage which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work. We use the new bounds to guide a greedy channel router, which manipulates exact adjacency information at every stage, allowing it to introduce jogs or doglegs when necessary for coupled noise reduction. Experimental results indicate that our algorithm compares favorably to previous work. The coupled noise is significantly reduced on benchmark instances.
284 citations
04 Nov 2001
TL;DR: This paper finds that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding.
Abstract: The propagation delay across long on-chip buses is increasingly becoming a limiting factor in high-speed designs. Crosstalk between adjacent wires on the bus may create a significant portion of this delay. Placing a shield wire between each signal wire alleviates the crosstalk problem but doubles the area used by the bus, an unacceptable consequence when the bus is routed using scarce top-level metal resources. Instead, we propose to employ data encoding to eliminate crosstalk delay within a bus. This paper presents a rigorous analysis of the theory behind "self-shielding codes", and gives the fundamental theoretical limits on the performance of codes with and without memory. Specifically, we find that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding.
271 citations
"A bus encoding technique for power ..." refers background in this paper
...The cross-talk is directly proportional to the number of adjacent transitions (1 0 or 0 1 transitions on adjacent wires at the same time) in the bus [12]....
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...Techniques to overcome cross-talk have been discussed [12, 14, 15]....
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01 Jan 1997
TL;DR: Analytical and experimental analyses are presented showing the improved performance of the encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding.
Abstract: In microprocessor-based systems, large power savings can be achieved through reduction of the transition activity of the on- and off-chip buses. This is because the total capacitance being switched when a voltage change occurs on a bus line is usually sensibly larger than the capacitive load that must be charged/discharged when internal nodes toggle. In this paper, we propose an encoding scheme which is suitable for reducing the switching activity on the lines of an address bus. The technique relies on the observation that, in a remarkable number of cases, patterns traveling onto address buses are consecutive. Under this condition it may therefore be possible, for the devices located at the receiving end of the bus, to automatically calculate the address to be received at the next clock cycle; consequently, the transmission of the new pattern can be avoided, resulting in an overall switching activity decrease. We present analytical and experimental analyses showing the improved performance of our encoding scheme when compared to both binary and Gray addressing schemes, the latter being widely accepted as the most efficient method for address bus encoding. We also propose power and timing efficient implementations of the encoding and the decoding logic, and we discuss the applicability of the technique to real microprocessor-based designs.
270 citations
"A bus encoding technique for power ..." refers background in this paper
...Techniques for minimizing the power dissipation in buses are well explored in the literature [1, 2, 3, 4, 5, 7, 8, 9]....
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