A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage
01 Dec 2017-pp 1-4
TL;DR: This paper addresses a CAD implementation for power-efficient power-distribution network (PDN) design for multi-voltage system-on-chip (SoC) in pre-layout stage to achieve higher power efficiency and satisfactory noise reduction in the PDN.
Abstract: This paper addresses a CAD implementation for power-efficient power-distribution network (PDN) design for multi-voltage system-on-chip (SoC) in pre-layout stage. High power efficiency and significant reduction in supply noise are achieved through optimization of different stages in PDN design for multi-voltage SoCs. The stages are a) selection of appropriate tree topology based on the multiple supply voltage (MSV), b) proper V dd allocation for different functional modules, c) appropriate decoupling capacitance (Decap) allocation at pre-layout stage. In this paper, each of these three criteria has been taken care of to achieve higher power efficiency and satisfactory noise reduction in the PDN. The proposed PDN design is implemented for 1024 point FFT core. Experimental results demonstrate the efficacy of our proposed technique. The power is maximally reduced by 90.29% and average peak noise has been maximally suppressed by 98.53% at the pre-layout stage after allocation of multiple V dd in the functional modules of FFT.
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672 citations
"A CAD approach for on-chip PDN with..." refers background in this paper
...With a desirable supply voltage level range throughout the chip, the PDN allow huge load current fluctuations [4]....
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...It lowers the insertion of the noise on the power-supply lines [4]....
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450 citations
"A CAD approach for on-chip PDN with..." refers background in this paper
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16 Apr 2007
TL;DR: A fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors and finds that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise.
Abstract: Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. These variations, primarily due to fast changes in supply current, can be attributed to architectural gating events that reduce power dissipation. In order to study this problem, the authors propose a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, the authors analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. They find that the activity of distinct cores in CMPs present several new design challenges when considering power supply noise, and they describe potentially problematic activity sequences that are unique to CMP architectures
200 citations
31 May 2005
TL;DR: This work proposes a methodology on top of a set of algorithms to exploit non-trivial voltage island boundaries for optimal power versus design cost trade-off under performance requirement, and shows a ten-fold improvement over current logical-boundary based industry approach.
Abstract: High power consumption not only leads to short battery life for handheld devices, but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer-grain power and performance trade-off. In this work we propose a methodology on top of a set of algorithms to exploit non-trivial voltage island boundaries for optimal power versus design cost trade-off under performance requirement. Our algorithms are efficient, robust and error-bounded, and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a ten-fold improvement of our method over current logical-boundary based industry approach.
82 citations
"A CAD approach for on-chip PDN with..." refers methods in this paper
...Then tentatively module-wise multi Vdd allocation is fulfilled using [11-14] as well as the estimation and allocation of the Decaps using equation (2) are done for the perspective modules....
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07 Apr 2002
TL;DR: Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change of the total chip area.
Abstract: With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in ASIC-like circuits. The adjoint sensitivity method is applied to calculate the first-order sensitivity of the power grid noise with respect to every decap. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change of the total chip area.
72 citations