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Proceedings ArticleDOI

A capacitor-less low-dropout regulator (LDO) architecture for wireless application

01 Mar 2017-pp 222-224

Abstract: Acapacitor-less low drop-out linear regulator with a new compensation technique is presented. A conventional LDO suffers intrinsic stability problem at low load currents and require a large offchip capacitor to make LDO stable. This off-chip capacitor occupies large area in the chip and thus not ideal for SoC applications. Many LDO architectures have been proposed recently but still some of them requires off-chip capacitor and suffers due to bandwidth limitation and requires additional complex circuits. The proposed LDO architecture with a compensation network provides solution to the above problem. The proposed LDO is simulated and verified in Cadence using 180 nm CMOS technology.
Topics: Low-dropout regulator (57%), Linear regulator (51%)
Citations
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Journal Article
TL;DR: It is demonstrated that in these LDOs the output voltage might be higher than the input reference voltage at minimum load current, and both the circuits begin "to follow" to achieve desired voltage with respect to load current depending on bias voltage.
Abstract: The transistor model is designed for outline of two different LDO Regulators having a differential stage stacked by current amplifier and the voltage feedback. The principal LDO has a consistent bias current. The LDOs were analysed to verify the transistors operations from weak inversion to strong inversion. It is demonstrated that in these LDOs the output voltage might be higher than the input reference voltage at minimum load current, and both the circuits begin "to follow" to achieve desired voltage with respect to load current depending on bias voltage. This paper additionally concentrates on outlining a particular LDO Regulator to fulfill the given requirements. The circuits were intended for 45 nm gpdk CMOS Technology and simulated in CADENCE Spectre tool.

01 Jan 2018-
TL;DR: This is the main report for Mattias Larsson's degree project for the Master’s program in System-on-Chip to design a modular MPSoC-unit (Multi Processor System ...
Abstract: This is the main report for Mattias Larsson’s degree project for the Master’s pro-gram in System-on-Chip. The main part of this project has been to design a modular MPSoC-unit (Multi Processor Syst ...

Cites background from "A capacitor-less low-dropout regula..."

  • ...Research is being done on how to implement an LDO without an external capacitance, for example Manikandan and Bindu [4], Lim et al. [5], and Luo and Siek [6]....

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  • ...Research is being done on how to implement an LDO without an external capacitance, for example Manikandan and Bindu [4], Lim et al....

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References
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Journal ArticleDOI
Gabriel A. Rincon-Mora1, P.E. Allen2Institutions (2)
Abstract: The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDO's are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low quiescent current LDO's at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero-load quiescent current flow of 23 /spl mu/A. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V, respectively.

609 citations


Journal ArticleDOI
Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

446 citations


Journal ArticleDOI
Abstract: This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%.

90 citations


"A capacitor-less low-dropout regula..." refers background in this paper

  • ...A power management system contains several sub systems including voltage regulators such as switching regulators and linear regulators [1]-[3]....

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Journal ArticleDOI
Sung-Wan Hong1, Gyu-Hyeong Cho2Institutions (2)
TL;DR: This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications that utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor- less LDOs.
Abstract: This paper presents a novel capacitor-less low-dropout regulator (LDO) for mobile applications. The proposed capacitor-less LDO utilizes multiple feedback loops to satisfy several design challenges for some mobile applications which were not considered in the previous capacitor-less LDOs. The proposed LDO has a wide bandwidth of 3.03 MHz at a load current of 150 mA with a bias current of 40 $\mu\mbox{A}$ , and the best line and load regulations of 0.0024%/V and 0.0000417%/mA, respectively, which are improvements over previously reported LDOs. This chip has a 100 mV dropout voltage with a 150 mA maximum load current. A total capacitance of 29 pF was used with a chip size of 0.279 $\mbox{mm}^{2}$ .

49 citations


"A capacitor-less low-dropout regula..." refers background in this paper

  • ...Some others require additional complex circuits [9]-[11] which lead to large power dissipation, low transient response and suffer by loading effects....

    [...]


Journal ArticleDOI
Mingyu Liu1, Donglai Zhang1, Zhicheng Zhou2Institutions (2)
Abstract: Envelope elimination and restoration technique and envelope tracking technique are proposed to enhance efficiency of radio frequency power amplifier (RFPA), and both of them take envelope amplifier (EA) as a high slew-rate variable voltage source. Serial linear-assisted switching converter, one of the solutions of EA, has benefits in high tracking bandwidth, high tracking accuracy, and relatively low switching losses. Among those many types of linear-assisted switching converter, the design of a linear regulator is rarely mentioned. This paper proposes a new design of linear regulator to supply a higher voltage and maintain high tracking bandwidth by dividing a linear regulator into four different parts. Beyond that, an input filter is recommended to increase the power supply rejection ratio (PSRR) of a linear regulator in high frequency, which is able to reduce the glitch caused by multilevel voltage power supply. An EA prototype is composed of the proposed linear regulator, the PSRR improvement filter, and the multilevel voltage power supply. To align signals, circular convolution is suggested as a modified algorithm. Experiments show that this prototype has a maximum output of 40 V, a tracking bandwidth of about 2 MHz for a full-range sinusoidal signal, and a tracking ability for OFDM envelope signal with a subcarrier up to 5 MHz.

22 citations


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20182