A Cascaded Gate Driver Architecture to Increase the Switching Speed of Power Devices in Series Connection
Summary (2 min read)
Introduction
- Hence, the medium-voltage grid and direct medium-voltage applications are becoming increasingly important.
- The cost and volume of the system can be increased due to the additional passive components in the clamp circuits.
- In such a way, the package is not sufficient since the parasitic capacitance introduced by the gate drive circuitry is one of the main causes of voltage unbalancing [10].
A. Gate Drive Power Supply Parasitic Capacitance
- In Fig. 1 is shown the classical gate drive circuitry where are highlighted the parasitic capacitances introduced by DCDC power supplies (Cps) and signal transmission functions of gate drivers (Ciso).
- The parasitic capacitances Cps and Ciso have the same dynamic influence on the system.
- Both GND and -VDC are isolated from each other.
- Therefore, isolated power converters are implemented in order to enable the isolation dedicated to the power supply parts, and optocouplers or optical fibers are used to isolate the paths for the control signals.
- Parasitic elements of the gate drive power supply and its connections.
B. Packaging/Layout Parasitic Capacitance
- To analyze the influence of parasitic capacitances introduced by the classical packaging/layout, a cross section of a simplified planar package and its main elements are shown in Fig. 3, which includes a base-plate, a DBC substrate, and two vertical series-connected SiC-MOSFETs.
- In Fig. 4 is shown an electrical scheme of two SiCMOSFETs connected in series, where Cpac1 and Cpac2 are the drain attached copper trace to ground parasitic capacitances associated to the devices S1 and S2, respectively.
- The capacitors Cpac can be estimated based on the planar capacitance formula (1).
- Ics since the devices are considered identical.
III. A NOVEL MULTI-STEP PACKAGING CONCEPT
- To compensate the parasitic currents that flow into the gate drive circuitry, a novel Multi-Step Packaging (MSP) concept is proposed in this work.
- As shown in Fig. 7 for two series-connected devices, three parasitic capacitances are introduced.
- In Fig. 8 is shown the electrical circuit configuration of the parasitic capacitances of the proposed MSP geometry and gate drive circuitry.
- The green zone represents the parasitic capacitance network introduced by the MSP, where the capacitances Cpac are located between the drain and source terminals of each device.
- The mathematical recurrence, expressed by Eq. (8) can be written to find the appropriate values of Cpac that compensate the Cps influence on the voltage balancing for N-seriesconnected devices.
IV. EXPERIMENTAL ANALYSES
- As shown in Fig. 11, a switching cell with two seriesconnected SiC-MOSFETs C2M0080120D (1200 V, 36 A), and one diode STPSC40H12CWL (1200V, 20A) has been used to investigate the influence of the proposed package concept on the voltage balancing under a total blocking voltage of 1 kV.
- As it is well known, the load current has a proportional influence on the switching speed [36], which in turns lead to great differences between Vds2 and Vds1.
- Analyzing the voltage balancing across the series-connected SiC-MOSFETs as shown in Fig. 15, it can be seen that the voltage sharing has a small variation with the load current.
- On the other hand, high values of Cpac increases the MSP performance in terms of voltage balancing since the mismatch between device intrinsic capacitances can be nullified by the capacitances Cpac.
- The study presented in [27] reveals that if the additional dielectric layers have small thermal resistances with respect to the other thermal resistance on the path of the heat flux, than, the MSP geometry has a limited impact on the distribution of the junction temperatures of the devices implemented on each step of the package.
V. CONCLUSION
- In this paper is analyzed a novel natural self-balancing voltage technique for series-connected SiC-MOSFETs.
- The propose method takes advantage of the parasitic capacitances introduced by a multi-step package to compensate the parasitic capacitances introduced by the gate driver circuitry and to reduce the voltage unbalancing across the power devices.
- In a first step, basics and concepts are explained using mathematical analysis.
- As expected, the proposed package shows better performance than the traditional planar package in terms of voltage balancing.
- The authors believe that the proposed packaging can be applied as a preventive solution.
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References
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Frequently Asked Questions (2)
Q2. What have the authors stated for future works in "A cascaded gate driver architecture to increase the switching speed of power devices in series connection" ?
This concept will be analyzed in future works.