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Proceedings Article•DOI•

A case for small row buffers in non-volatile main memories

Justin Meza1, Jing Li2, Onur Mutlu1•
Carnegie Mellon University1, IBM2
30 Sep 2012-Vol. 2012, pp 484-485
TL;DR: It is found that on a multi-core system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some NVM technologies, leads to improved performance.
Abstract: DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping schemes that improve memory parallelism lead to only a small amount of the buffered data to be accessed. This makes buffering large amounts of data on every memory array access energy-inefficient; yet organizing DRAM chips to buffer small amounts of data is costly, as others have shown [11]. Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional area penalty and/or design complexity. In this work, we discuss and evaluate architectural changes to enable small row buffers at a low cost in NVMs. We find that on a multi-core system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some NVM technologies, leads to improved performance.

Summary (2 min read)

Jump to: [Introduction] – [II. MOTIVATION] – [III. A SMALL ROW BUFFER NVM ARCHITECTURE] and [IV. RESULTS]

Introduction

  • Abstract—DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low.
  • Emerging non-volatile memories (NVMs) such as PCM, STT-RAM, and RRAM, however, do not have destructive read operations, opening up opportunities for employing small row buffers without incurring additional area penalty and/or design complexity.
  • Over time, this charge leaks, causing the stored data to be lost.
  • As a result, the performance benefit of large row buffers may decrease in multi-core systems.

II. MOTIVATION

  • Emerging NVM technologies have several promising attributes compared to existing memory technologies such as SRAM (used in on-chip caches), DRAM, and Flash.
  • NVMs provide cost advantages compared to SRAM and DRAM, and latency advantages compared to Flash.
  • Typical DRAM chip micro-architectures (JEDEC-standard DDRtype SDRAM) are divided into banks that consist of rows and columns .
  • Comparing the 1- and 8-core row-interleaved data, the authors see that while row interleaving does enable more row buffer locality, its benefits diminish as memory system contention increases with more cores: row buffer hit rate is less than 50% for row interleaving even with large, 1KB rows.

III. A SMALL ROW BUFFER NVM ARCHITECTURE

  • Figure 1(b) shows the organization of their NVM architecture.
  • Compared to a traditional DRAM organization, the physical placement of the row buffer and the column multiplexer (part of the I/O gating circuitry in DRAM designs) are swapped in the data path (shown in gray).
  • This rearrangement makes better use of resources by sharing a smaller number of sense amplifiers (the devices which store bits in the row buffer) among multiple bitlines.
  • Note that this is not possible in DRAM (without reducing the row size) because a sense amplifier for each bit in the row is required in DRAM to restore the charge of the cell after it is read.
  • Unlike DRAM, however, their organization requires decoding both the row address and the column address during a RAS command, so that only a subset of the row containing the bits of interest will be selected, sensed, and stored in the row buffer.

IV. RESULTS

  • The authors modify their memory simulator timings according to those in Table I for PCM and STT-RAM.
  • The authors evaluate 31 multiprogrammed workloads composed of SPEC, TPC, and STREAM benchmarks.
  • Note that this reduction is achieved despite worse underlying technology parameters 2For more details, please refer to their accompanying tech report [5].
  • For a given memory technology, reducing the row buffer size does not greatly affect system performance due to the already low row buffer locality present on their multi-core system .
  • NVM cells have a limited lifetime in terms of the number of times they can be written to before their ability to store data fails, also known as Durability.

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A Case for Small Row Buffers in Non-Volatile Main Memories
Justin Meza
∗
Jing Li
†
Onur Mutlu
∗
∗
Carnegie Mellon University
†
IBM T.J. Watson Research Center
{meza,onur}@cmu.edu jli@us.ibm.com
Abstract—DRAM-based main memories have read operations that
destroy the read data, and as a result, must buffer large amounts of data
on each array access to keep chip costs low. Unfortunately, system-level
trends such as increased memory contention in multi-core architectures
and data mapping schemes that improve memory parallelism lead to only
a small amount of the buffered data to be accessed. This makes buffering
large amounts of data on every memory array access energy-inefficient;
yet organizing DRAM chips to buffer small amounts of data is costly, as
others have shown [11].
Emerging non-volatile memories (NVMs) such as PCM, STT-RAM,
and RRAM, however, do not have destructive read operations, opening
up opportunities for employing small row buffers without incurring
additional area penalty and/or design complexity. In this work, we
discuss and evaluate architectural changes to enable small row buffers
at a low cost in NVMs. We find that on a multi-core system, reducing
the row buffer size can greatly reduce main memory dynamic energy
compared to a DRAM baseline with large row sizes, without greatly
affecting endurance, and for some NVM technologies, leads to improved
performance.
I. INTRODUCTION
Modern main memory is composed of dynamic random-access
memory (DRAM). A DRAM cell stores data as charge on a capacitor.
Over time, this charge leaks, causing the stored data to be lost. To
prevent this, data stored in DRAM must be periodically read out and
rewritten, a process called refreshing. In addition, reading data stored
in a DRAM cell destroys its state, requiring data to be later restored,
leading to increased cell access time and energy. For this reason,
DRAM devices require buffering data which are read. To keep costs
low, the buffering circuitry in DRAM devices is amortized among
large rows of cells, in peripheral storage called the row buffer, at
least one per bank [2]. Refreshing data and buffering large amounts of
data wastes energy in DRAM devices, causing main memory power
to constitute a significant fraction of the total system power.
Data fetched into the row buffer, however, can be accessed at much
lower latencies and less energy than accessing the DRAM memory
array. Therefore, large row buffer sizes can improve performance
and efficiency if many accesses can be served in the same row.
Unfortunately, there are several reasons why such row buffer locality
can be low in systems: (1) some applications inherently do not have
significant locality within rows (e.g., random access applications),
(2) as more cores are placed on chip, applications running on those
cores interfere with each other in the row buffers, leading to reduced
locality, especially if the memory scheduling policy is unaware of
applications’ interference in the row buffers [7], as also observed
by others [10, 11], and (3) interleaving techniques that improve
parallelism in the memory system (e.g., cache block interleaving)
tend to reduce row buffer locality because they stripe consecutive
cache blocks across different banks. As a result, the performance
benefit of large row buffers may decrease in multi-core systems.
New non-volatile memory (NVM) technologies, such as phase-
change memory (PCM), spin-transfer torque RAM (STT-RAM), and
resistive RAM (RRAM), on the other hand, provide non-destructive
reads and do not require refreshing and restoring their data after
sensing. This is because NVMs do not store their data as charge, and
thus their data persists after being read. This not only eliminates the
refresh problem of DRAM devices but also opens up opportunities for
employing smaller row buffers in NVMs without incurring additional
area penalty and/or design complexity.
II. MOTIVATION
Emerging NVM technologies have several promising attributes
compared to existing memory technologies such as SRAM (used in
on-chip caches), DRAM, and Flash. For example, NVMs provide cost
advantages compared to SRAM and DRAM, and latency advantages
compared to Flash. Importantly, these NVMs feature non-destructive
read operations, which DRAM does not have (i.e., data sensing does
not destroy the contents of cells).
Typical DRAM chip micro-architectures (JEDEC-standard DDR-
type SDRAM) are divided into banks that consist of rows (wordlines)
and columns (bitlines). Due to physical pin limitations, all the
information required to service a memory request must be supplied
over multiple commands. The Row Address Strobe (RAS) command
sends the row and bank address to select one of the banks and a row
within that bank. Then, an entire row (usually 1 to 2KB per chip)
is read out into latch-based sense amplifiers which comprise the row
buffer [2]. The Column Address Strobe (CAS) command then selects
a subset (i.e., column) of data from the row buffer (8B in a DDR3
×8 device [6]). Thus, a DRAM access first fetches many kilobytes
of data into the row buffer (RAS) and, in the worst case, uses only
a tiny portion of it (CAS). If multiple columns of the row buffer are
needed, multiple consecutive CAS commands can be issued, which
amortizes the cost of fetching the large row into the row buffer.
To illustrate how much buffered data is actually used in real
applications, Figure 1a shows average row buffer locality (row hit
rate) when employing various row buffer sizes on several system con-
figurations using the FR-FCFS scheduling policy [8].
1
In particular,
we show 1- and 8-core systems employing two different schemes
for mapping data in main memory: (1) row interleaving, which
places consecutive memory addresses in the same row, and (2) block
interleaving, which stripes data in consecutive memory addresses
(usually cache blocks) across different banks. Row interleaving helps
exploit row buffer locality by enabling data with spatial locality
to reside in the same row buffer, while block interleaving aims
to improve memory parallelism by enabling concurrent access of
memory channels/banks for consecutive memory addresses.
Comparing the 1- and 8-core row-interleaved data, we see that
while row interleaving does enable more row buffer locality, its
benefits diminish as memory system contention increases with more
cores: row buffer hit rate is less than 50% for row interleaving even
with large, 1KB rows. Block interleaving reduces row buffer locality
over row interleaving, to less than 10% in the 8-core case. While
it is clear that row locality is lower on multi-core systems, what
is less obvious is how row buffer size affects system-level tradeoffs,
such as energy-efficiency, performance, and durability, in NVM main
memories. This work evaluates these tradeoffs.
8B 16B 32B 64B 128B 256B 512B
1KB
Per DRAM-Chip Row Buffer Size
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Row Buffer Locality
1-core, row interleaved
8-core, row interleaved
1-core, cache block interleaved
8-core, cache block interleaved
(a)
Bank N
Bank 2
Bank 1
Bank 0
Memory Array
Row Buffer
Column Decoder
and Multiplexer
Row Decoder
...
...
...
(b)
Fig. 1: Row size affects row locality (a); our NVM architecture (b).
1
Application-aware memory request scheduling policies (e.g., [1, 3, 7])
provide better performance, but they can reduce row buffer locality.
1
8B 16B 32B 64B 128B 256B 512B
1KB
Baseline
Per DRAM-Chip Row Buffer Size
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Normalized Memory Energy
STT-RAM
DRAM
PCM
(a) Memory energy with block interleaving.
8B 16B 32B 64B 128B 256B 512B
1KB
Per DRAM-Chip Row Buffer Size
0
1
2
3
4
5
Weighted Speedup
STT-RAM
DRAM
PCM
(b) Performance with block interleaving.
8B 16B 32B 64B 128B 256B 512B
1KB
Per DRAM-Chip Row Buffer Size
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Normalized Writes
No cache
32MB cache
(c) Writes with and without a 32MB cache.
Fig. 2: Multi-core results for energy (normalized to DRAM with 1KB rows), performance, and number of writes (normalized to 1KB rows).
III. A SMALL ROW BUFFER NVM ARCHITECTURE
Figure 1(b) shows the organization of our NVM architecture. Com-
pared to a traditional DRAM organization, the physical placement of
the row buffer and the column multiplexer (part of the I/O gating
circuitry in DRAM designs) are swapped in the data path (shown in
gray). This rearrangement makes better use of resources by sharing a
smaller number of sense amplifiers (the devices which store bits in the
row buffer) among multiple bitlines. Note that this is not possible in
DRAM (without reducing the row size) because a sense amplifier for
each bit in the row is required in DRAM to restore the charge of the
cell after it is read. Unlike DRAM, however, our organization requires
decoding both the row address and the column address during a RAS
command, so that only a subset of the row containing the bits of
interest will be selected, sensed, and stored in the row buffer. During
a CAS command, the data bits from the row buffer corresponding to
the desired column are further selected by the I/O gating circuitry
and sent to a prefetch buffer.
2
While related prior work [4] employed multiple, narrow rows
in a PCM main memory for reducing array reads and writes, it
focused on (1) a traditional DRAM data path design, (2) an iso-
area reorganization, requiring more area overhead than our technique
which employs smaller row buffers, and (3) assumed a standard
DRAM protocol for device access.
IV. RESULTS
We developed a cycle-accurate DDR3 memory simulator which we
use as part of an in-house x86 multi-core simulator, whose front-end
is based on Pin. We modify our memory simulator timings according
to those in Table I for PCM and STT-RAM. We show results for an
8-core system with different memories and row buffer sizes, though
reducing row buffer size in DRAM incurs significant area overhead
and chip cost, as discussed in [10, 11], which we do not evaluate.
We evaluate 31 multiprogrammed workloads composed of SPEC,
TPC, and STREAM benchmarks. We will focus on a DRAM chip
micro-architecture with 1KB row buffers and block interleaving as
our baseline (our findings are similar for row interleaving [5]).
Technology Energy (Read/Write) Latency (Read/Write)
PCM 2×/100× 5×/10×
STT-RAM 0.5×/1× 1×/1×
TABLE I: NVM array parameters, relative to DRAM.
Energy (Figure 2a): In all cases, reducing the row buffer size can
significantly reduce memory energy consumption, though there are
diminishing marginal returns. The diminishing marginal returns are
because, as the row buffer size decreases, memory energy becomes
dominated by the energy required to transfer data between the row
buffer and I/O pads during read and write operations.
A modest row buffer size of 64B per chip leads to 47%/67%
less main memory energy for PCM/STT-RAM, compared to an all-
DRAM main memory with large rows (1KB per chip). Note that this
reduction is achieved despite worse underlying technology parameters
2
For more details, please refer to our accompanying tech report [5].
than DRAM (cf. Table I) because the energy saved by reducing the
row buffer size more than makes up for the higher average memory
array access energy. Hence, an NVM main memory with smaller
row buffers can significantly reduce memory energy consumption
compared to a DRAM baseline with large row buffers.
Performance (Figure 2b): We evaluate the performance of our
system using the weighted speedup metric [9] (higher is better). For
a given memory technology, reducing the row buffer size does not
greatly affect system performance due to the already low row buffer
locality present on our multi-core system (cf. Figure 1a). Interestingly,
with similar technology-dependent timing parameters as DRAM, an
STT-RAM main memory can achieve better performance because our
new organization enables a more efficient access protocol (detailed
in [5]) which eliminates the precharge delay incurred on row buffer
misses, and relaxes the t
RRD
and t
FAW
timing parameters to enable
more banks to be accessed simultaneously.
Durability (Figure 2c): NVM cells have a limited lifetime in terms
of the number of times they can be written to before their ability
to store data fails. We examine the effects of different row buffer
sizes on device durability with and without a small 32MB e-DRAM
cache to a PCM main memory. We find that with or without a cache,
decreasing the row buffer size has only a small effect on the number
of NVM writes performed due to the low row buffer locality present
in the system. In contrast, the addition of a reasonably-sized e-DRAM
cache has a large impact on the reduction of writes, decreasing the
number of writes by 39% to 47% across the various row buffer sizes.
V. CONCLUSIONS
We showed that on a multi-core system, reducing the row buffer
size can greatly reduce main memory dynamic energy compared
to a DRAM baseline with large rows, without greatly affecting
performance and durability. Our future work includes exploring
architectural techniques which effectively leverage small row buffer
sizes for improved performance and energy-efficiency.
REFERENCES
[1] Y. Kim et al. ATLAS: A scalable and high-performance scheduling
algorithm for multiple memory controllers. HPCA ’10.
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[3] Y. Kim et al. Thread cluster memory scheduling: Exploiting differences
in memory access behavior. MICRO ’10.
[4] B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change
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[5] J. Meza, J. Li, and O. Mutlu. A case for small row buffers in non-volatile
main memories. http://safari.ece.cmu.edu/tr/tr-2012-002.pdf.
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[8] S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens.
Memory access scheduling. ISCA ’00.
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2
Citations
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Proceedings Article•DOI•
Architecting STT Last-Level-Cache for performance and energy improvement

[...]

Fazal Hameed1, Mehdi B. Tahoori1•
Karlsruhe Institute of Technology1
15 Mar 2016
TL;DR: This work proposes two row buffer bypass policies and an alternative row buffer organization to reduce the number of row buffer conflicts in STT-RAM based Last-Level-Cache architectures and reduces the average energy consumption by 19.5%.
Abstract: Spin Transfer Torque Random Access Memory (STT-RAM) is a promising alternative to DRAM memory for Last-Level-Cache due to low leakage power and the absence of refresh energy Recent research has illustrated the performance and energy benefits of STT-RAM over DRAM memory via reducing the number of row buffer conflicts However, state-of-the-art techniques do not fully exploit the cache access patterns which can lead to a reduced performance and energy efficiency We therefore propose two row buffer bypass policies and an alternative row buffer organization to reduce the number of row buffer conflicts in STT-RAM based Last-Level-Cache architectures We evaluate our policies and organization for different combinations of SPEC2006 benchmarks and compare their performance and energy with recent proposal for STT-RAM based memory Our proposal reduces the average energy consumption by 195% compared to the state-of-the-art

11 citations

Proceedings Article•DOI•
Efficient STT-RAM last-level-cache architecture to replace DRAM cache

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Fazal Hameed1, Christian Menard1, Jeronimo Castrillon1•
Dresden University of Technology1
02 Oct 2017
TL;DR: A Selective Read Policy for STT-RAM is proposed that only fetches those cache lines into the row buffer that are likely to be reused that reduces the number of cache line reads and thereby reduces the energy consumption.
Abstract: Recent research has proposed die-stacked Last Level Cache (LLC) to overcome the Memory Wall. Lately, Spin-Transfer-Torque Random Access Memory (STT-RAM) caches have been recommended as they provide improved energy efficiency compared to DRAM caches. However, the recently proposed STT-RAM cache architecture unnecessarily dissipates energy by fetching unneeded cache lines into the row buffer. In this paper, we propose a Selective Read Policy for STT-RAM. This is policy only fetches those cache lines into the row buffer that are likely to be reused. This is reduces the number of cache line reads and thereby reduces the energy consumption. Further, we propose two key performance optimizations namely Row Buffer Tags Bypass Policy and LLC Data Cache. Both optimizations reduce the LLC access latency and therefore improve the overall performance. For evaluation, we implement our proposed architecture in the Zesto simulator and run different combinations of SPEC2006 benchmarks on an 8-core system. We show that our synergetic policies reduce the average LLC dynamic energy consumption by 72.6% and improve the system performance by 1.3% compared to the recently proposed STT-RAM LLC. Compared to the state-of-the-art DRAM LLC, our architecture reduces the LLC dynamic energy consumption by 90.6% and improves system performance by 1.4%.

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Cites background from "A case for small row buffers in non..."

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WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders

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Leonid Yavits1, Lois Orosa2, Suyash Mahar3, João Dinis Ferreira2, Mattan Erez4, Ran Ginosar1, Onur Mutlu2 •
Technion – Israel Institute of Technology1, ETH Zurich2, Indian Institute of Technology Roorkee3, University of Texas at Austin4
06 Oct 2020-arXiv: Hardware Architecture
TL;DR: The key idea of WoLFRaM is to use PRAD for implementing a new efficient wear-leveling mechanism that remaps write accesses to random physical locations on the fly, and a new effiCient fault tolerance mechanism that recovers from faults by remapping failed memory blocks to available physical locations.
Abstract: Resistive memories have limited lifetime caused by limited write endurance and highly non-uniform write access patterns. Two main techniques to mitigate endurance-related memory failures are 1) wear-leveling, to evenly distribute the writes across the entire memory, and 2) fault tolerance, to correct memory cell failures. However, one of the main open challenges in extending the lifetime of existing resistive memories is to make both techniques work together seamlessly and efficiently. To address this challenge, we propose WoLFRaM, a new mechanism that combines both wear-leveling and fault tolerance techniques at low cost by using a programmable resistive address decoder (PRAD). The key idea of WoLFRaM is to use PRAD for implementing 1) a new efficient wear-leveling mechanism that remaps write accesses to random physical locations on the fly, and 2) a new efficient fault tolerance mechanism that recovers from faults by remapping failed memory blocks to available physical locations. Our evaluations show that, for a Phase Change Memory (PCM) based system with cell endurance of 108 writes, WoLFRaM increases the memory lifetime by 68% compared to a baseline that implements the best state-of-the-art wear-leveling and fault correction mechanisms. WoLFRaM's average / worst-case performance and energy overheads are 0.51% / 3.8% and 0.47% / 2.1% respectively.

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Cites background from "A case for small row buffers in non..."

  • ...Because all subarrays in a bank share the row bu er [38, 50, 51, 70, 71, 115] and the swap bu er, the remap and swap operation of each individual block is similar to the remap and swap operation within a subarray....

    [...]

  • ...The target memory block, typically 256B to 1kB [18, 45, 50, 53, 55, 70, 71, 88], is individually addressable within a subarray, while a subarray is individually addressable within a bank....

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  • ...This is possible because sense ampli ers and row bu ers are decoupled in non-volatile memories [38, 50, 51, 70, 71, 115]....

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Journal Article•DOI•
Building and Optimizing MRAM-Based Commodity Memories

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Jue Wang1, Xiangyu Dong2, Yuan Xie3•
Pennsylvania State University1, Qualcomm2, University of California, Santa Barbara3
08 Dec 2014-ACM Transactions on Architecture and Code Optimization
TL;DR: Four techniques to enable and optimize an LPDDRx-compatible MRAM solution are proposed: ComboAS to solve the pin incompatibility; DynLat to avoid unnecessary access latencies, and EarlyPA and BufW to further improve performance by exploiting the MRAM unique features of non-destructive read and independent write path.
Abstract: Emerging non-volatile memory technologies such as MRAM are promising design solutions for energy-efficient memory architecture, especially for mobile systems. However, building commodity MRAM by reusing DRAM designs is not straightforward. The existing memory interfaces are incompatible with MRAM small page size, and they fail to leverage MRAM unique properties, causing unnecessary performance and energy overhead. In this article, we propose four techniques to enable and optimize an LPDDRx-compatible MRAM solution: ComboAS to solve the pin incompatibility; DynLat to avoid unnecessary access latencies; and EarlyPA and BufW to further improve performance by exploiting the MRAM unique features of non-destructive read and independent write path. Combining all these techniques together, we boost the MRAM performance by 17p and provide a DRAM-compatible MRAM solution consuming 21p less energy.

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Cites background or methods or result from "A case for small row buffers in non..."

  • ...When the number of cores is increased, the page-hit ratio of the main memory system is decreased as the number of processes simultaneously accessing memory goes up, which is also proved in some previous works [Udipi et al. 2010; Meza et al. 2012a]....

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  • ...Spin-transfer torque magnetic RAM (STT-MRAM or MRAM2) is an attractive emerging nonvolatile memory (NVM) technology, and its power-saving opportunities have been heavily exploited [Meza et al. 2012a; Kultursay et al. 2013; Meza et al. 2012b]....

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  • ...The other technique they proposed [Meza et al. 2012b] issues the precharge as soon as sensing completes, and it sends the row address in PRE commands....

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  • ...DOI: http://dx.doi.org/10.1145/2667105...

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References
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Proceedings Article•DOI•
Architecting phase change memory as a scalable dram alternative

[...]

Benjamin C. Lee1, Engin Ipek1, Onur Mutlu2, Doug Burger1•
Microsoft1, Carnegie Mellon University2
20 Jun 2009
TL;DR: This work proposes, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM.
Abstract: Memory scaling is in jeopardy as charge storage and sensing mechanisms become less reliable for prevalent memory technologies, such as DRAM. In contrast, phase change memory (PCM) storage relies on scalable current and thermal mechanisms. To exploit PCM's scalability as a DRAM alternative, PCM must be architected to address relatively long latencies, high energy writes, and finite endurance.We propose, crafted from a fundamental understanding of PCM technology parameters, area-neutral architectural enhancements that address these limitations and make PCM competitive with DRAM. A baseline PCM system is 1.6x slower and requires 2.2x more energy than a DRAM system. Buffer reorganizations reduce this delay and energy gap to 1.2x and 1.0x, using narrow rows to mitigate write energy and multiple rows to improve locality and write coalescing. Partial writes enhance memory endurance, providing 5.6 years of lifetime. Process scaling will further reduce PCM energy costs and improve endurance.

1,568 citations

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Memory access scheduling

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Scott Rixner1, William J. Dally2, Ujval J. Kapasi2, Peter Mattson2, John D. Owens2 •
Massachusetts Institute of Technology1, Stanford University2
01 May 2000
TL;DR: This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure.
Abstract: The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of contemporary DRAM chips. There is nearly an order of magnitude difference in bandwidth between successive references to different columns within a row and different rows within a bank. This paper introduces memory access scheduling, a technique that improves the performance of a memory system by reordering memory references to exploit locality within the 3-D memory structure. Conservative reordering, in which the first ready reference in a sequence is performed, improves bandwidth by 40% for traces from five media benchmarks. Aggressive reordering, in which operations are scheduled to optimize memory bandwidth, improves bandwidth by 93% for the same set of applications. Memory access scheduling is particularly important for media processors where it enables the processor to make the most efficient use of scarce memory bandwidth.

1,009 citations

Journal Article•DOI•
Symbiotic jobscheduling for a simultaneous multithreaded processor

[...]

Allan Snavely1, Dean M. Tullsen1•
University of California, San Diego1
12 Nov 2000
TL;DR: It is demonstrated that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler, and that a small sample of the possible schedules is sufficient to identify a good schedule quickly.
Abstract: Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there are more jobs in the system than there is hardware to support simultaneous execution, the operating system scheduler must choose the set of jobs to coscheduleThis paper demonstrates that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler. Thus, the full benefits of SMT hardware can only be achieved if the scheduler is aware of thread interactions. Here, a mechanism is presented that allows the scheduler to significantly raise the performance of SMT architectures. This is done without any advance knowledge of a workload's characteristics, using sampling to identify jobs which run well together.We demonstrate an SMT jobscheduler called SOS. SOS combines an overhead-free sample phase which collects information about various possible schedules, and a symbiosis phase which uses that information to predict which schedule will provide the best performance. We show that a small sample of the possible schedules is sufficient to identify a good schedule quickly. On a system with random job arrivals and departures, response time is improved as much as 17% over a schedule which does not incorporate symbiosis.

619 citations

Proceedings Article•DOI•
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers

[...]

Yoongu Kim1, Dongsu Han1, Onur Mutlu1, Mor Harchol-Balter1•
Carnegie Mellon University1
01 Apr 2010
TL;DR: It is shown that the implementation of least-attained-service thread prioritization reduces the time the cores spend stalling and significantly improves system throughput, and ATLAS's performance benefit increases as the number of cores increases.
Abstract: Modern chip multiprocessor (CMP) systems employ multiple memory controllers to control access to main memory. The scheduling algorithm employed by these memory controllers has a significant effect on system throughput, so choosing an efficient scheduling algorithm is important. The scheduling algorithm also needs to be scalable — as the number of cores increases, the number of memory controllers shared by the cores should also increase to provide sufficient bandwidth to feed the cores. Unfortunately, previous memory scheduling algorithms are inefficient with respect to system throughput and/or are designed for a single memory controller and do not scale well to multiple memory controllers, requiring significant finegrained coordination among controllers. This paper proposes ATLAS (Adaptive per-Thread Least-Attained-Service memory scheduling), a fundamentally new memory scheduling technique that improves system throughput without requiring significant coordination among memory controllers. The key idea is to periodically order threads based on the service they have attained from the memory controllers so far, and prioritize those threads that have attained the least service over others in each period. The idea of favoring threads with least-attained-service is borrowed from the queueing theory literature, where, in the context of a single-server queue it is known that least-attained-service optimally schedules jobs, assuming a Pareto (or any decreasing hazard rate) workload distribution. After verifying that our workloads have this characteristic, we show that our implementation of least-attained-service thread prioritization reduces the time the cores spend stalling and significantly improves system throughput. Furthermore, since the periods over which we accumulate the attained service are long, the controllers coordinate very infrequently to form the ordering of threads, thereby making ATLAS scalable to many controllers. We evaluate ATLAS on a wide variety of multiprogrammed SPEC 2006 workloads and systems with 4–32 cores and 1–16 memory controllers, and compare its performance to five previously proposed scheduling algorithms. Averaged over 32 workloads on a 24-core system with 4 controllers, ATLAS improves instruction throughput by 10.8%, and system throughput by 8.4%, compared to PAR-BS, the best previous CMP memory scheduling algorithm. ATLAS's performance benefit increases as the number of cores increases.

439 citations

Proceedings Article•DOI•
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

[...]

Yoongu Kim1, Michael K. Papamichael1, Onur Mutlu1, Mor Harchol-Balter1•
Carnegie Mellon University1
04 Dec 2010
TL;DR: This paper presents a new memory scheduling algorithm that addresses system throughput and fairness separately with the goal of achieving the best of both, and evaluates TCM on a wide variety of multiprogrammed workloads and compares its performance to four previously proposed scheduling algorithms, finding that TCM achieves both the best system throughputand fairness.
Abstract: In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. Previously proposed memory scheduling algorithms are predominantly optimized for only one of these objectives: no scheduling algorithm provides the best system throughput and best fairness at the same time. This paper presents a new memory scheduling algorithm that addresses system throughput and fairness separately with the goal of achieving the best of both. The main idea is to divide threads into two separate clusters and employ different memory request scheduling policies in each cluster. Our proposal, Thread Cluster Memory scheduling (TCM), dynamically groups threads with similar memory access behavior into either the latency-sensitive (memory-non-intensive) or the bandwidth-sensitive (memory-intensive) cluster. TCM introduces three major ideas for prioritization: 1) we prioritize the latency-sensitive cluster over the bandwidth-sensitive cluster to improve system throughput, 2) we introduce a ``niceness'' metric that captures a thread's propensity to interfere with other threads, 3) we use niceness to periodically shuffle the priority order of the threads in the bandwidth-sensitive cluster to provide fair access to each thread in a way that reduces inter-thread interference. On the one hand, prioritizing memory-non-intensive threads significantly improves system throughput without degrading fairness, because such ``light'' threads only use a small fraction of the total available memory bandwidth. On the other hand, shuffling the priority order of memory-intensive threads improves fairness because it ensures no thread is disproportionately slowed down or starved. We evaluate TCM on a wide variety of multiprogrammed workloads and compare its performance to four previously proposed scheduling algorithms, finding that TCM achieves both the best system throughput and fairness. Averaged over 96 workloads on a 24-core system with 4 memory channels, TCM improves system throughput and reduces maximum slowdown by 4.6%/38.6% compared to ATLAS (previous work providing the best system throughput) and 7.6%/4.6% compared to PAR-BS (previous work providing the best fairness).

375 citations

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Frequently Asked Questions (2)
Q1. What have the authors contributed in "A case for small row buffers in non-volatile main memories" ?

In this work, the authors discuss and evaluate architectural changes to enable small row buffers at a low cost in NVMs. The authors find that on a multi-core system, reducing the row buffer size can greatly reduce main memory dynamic energy compared to a DRAM baseline with large row sizes, without greatly affecting endurance, and for some NVM technologies, leads to improved performance. 

Their future work includes exploring architectural techniques which effectively leverage small row buffer sizes for improved performance and energy-efficiency.