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Journal ArticleDOI

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

01 Jan 2018-IEEE Transactions on Electron Devices (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 65, Iss: 1, pp 299-307
TL;DR: Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field effect transistors (TFETs) is developed in this article.
Abstract: Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.
Citations
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Journal ArticleDOI
Bin Lu1, Hongliang Lu1, Yuming Zhang1, Yimen Zhang1, Xiaoran Cui1, Zhijun Lv1, Chen Liu1 
TL;DR: Based on an analytical surface potential model incorporating the channel inversion carriers, a physics-based terminal capacitance model with closed-form solutions for a hetero-gate-dielectric (HGD) tunnel field-effect transistor (TFET) is developed for the first time in this article.
Abstract: Based on an analytical surface potential model incorporating the channel inversion carriers, a physics-based terminal capacitance model with closed-form solutions for a hetero-gate-dielectric (HGD) tunnel field-effect transistor (TFET) is developed for the first time. Good agreements between the proposed model and the numerical simulations have been achieved in all operation regimes and for different HGD structures. The developed model without involving any iterative process can be easily applied to the widely used SPICE simulations and would be helpful for the transient performance of TFET-based circuits.

15 citations


Cites background from "A Charge-Based Capacitance Model fo..."

  • ...According to our previous work, the channel carrier density can be expressed as ND exp(− CD/Vt ), where Vt is the thermal voltage [20]....

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Journal ArticleDOI
TL;DR: A novel planar architecture for tunnel field-effect transistors with better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works is proposed.
Abstract: A novel planar architecture is proposed for tunnel field-effect transistors (TFETs). The advantages of this architecture are exhibited, taking the InAs/Si TFET as an example, and the effects of different device parameters are analyzed in detail. Owing to the gate field being parallel to the tunneling interface, the gate control is enhanced, and a better electrical performance is obtained. Moreover, different from a conventional TFET, in which the effective tunneling area and current can hardly be modulated by the gate length, in our proposed device, the effective tunneling area and current can be adjusted depending on the actual requirements of circuit design, which increases the flexibility of TFET-based circuit design. In addition, the device architecture can also be extended to other materials, such as Ge/Si and GaSb/InAs, and thus be used for both n-type and p-type devices. The results show that the complementary digital inverter structure with InAs/Si as the n-type TFET and Ge/Si as the p-type TFET would be helpful for future ultralow power applications. This proposed structure without any complicated fabrication steps shows better compatibility with CMOS technology compared to other TFETs with heterojunction and structural innovations presented in theoretical works.

11 citations


Cites background from "A Charge-Based Capacitance Model fo..."

  • ...TFETs have been intensively investigated in recent years and are expected to be seen in semiconductor products after 2022 [5], [6]....

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Journal ArticleDOI
TL;DR: In this article, an explicit analytical model for surface potential, capacitance and drain current is proposed for double-gate tunnel field effect transistor (DG-TFET), where accumulation of charge carriers take place with the applied gate bias.

9 citations

Journal ArticleDOI
TL;DR: In this article, an N+ doped buried drain is proposed to form a reverse biased p-n junction with the source and effectively cut the leakage current path off, and the InAs/GaSb line-tunneling field effect transistor (LTFET) with this buried drain technique exhibits high ON-state current and low sub-threshold swing (SS) for five decades of current.
Abstract: The combination of the InAs/GaSb heterojunction and the line-tunneling mechanism is considered as one of the most promising approaches to simultaneously obtain high ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and low subthreshold swing (SS) in tunneling field effect transistors (TFETs). However, in an InAs/GaSb line-tunneling field effect transistor (LTFET), the isolation between the source and the drain is a big issue. The leakage current path could lead to complete loss of the OFF-state characteristics in extreme cases. The “cantilever” or “airbridge” structure is usually introduced to cutoff the leakage path. However, it also induces serious reliability problems and brings additional process complexity. In this article, an N+ doped buried drain is first proposed to form a reverse biased p-n junction with the $\text{P}\boldsymbol +$ source and effectively cuts the leakage current path off. The InAs $\boldsymbol /$ GaSb LTFETs with this buried drain technique exhibits ${I}_{ \mathrm{\scriptscriptstyle ON}} \boldsymbol / {I}_{ \mathrm{\scriptscriptstyle OFF}} > {10}^{{7}}$ and SS $\boldsymbol /$ dec for five decades of current. Besides the excellent performance, the buried drain technique keeps the device planar and brings no additional fabrication complexity, which is of great significance for future experimental investigation and the low power applications.

9 citations

Journal ArticleDOI
TL;DR: In this article, the characteristics of a hetero-dielectric ferroelectric tunnel (HD-FeTFET) were investigated, and the performance of the proposed structure was compared with conventional tunnel field effect transistors (TFETs) and ferro-electric TFETs.
Abstract: We have investigated the characteristics of a hetero-dielectric ferroelectric tunnel (HD-FeTFET). Extensive simulations show that using a hetero-dielectric gate architecture in the lateral direction (non-ferroelectric/ferroelectric/non-ferroelectric) results in more desirable analog/RF characteristics. The proposed structure is compared with conventional tunnel field effect transistors (TFETs) and ferroelectric TFET (FeTFET). Simulation results manifest that HD-FeTFET is superior to other compared structures, and benefits from both ferroelectric and hetero-dielectric structure. Negative capacitance effect in ferroelectric causes a step-up voltage transformer, as a result the subthreshold swing decreases. Owing to two different dielectric constants in the hetero-dielectric structure, the electric field enhances; thereby, the on-state current increases. In this paper, important analog/RF figures of merit, such as cut-off frequency (fT), maximum oscillation frequency (fmax), transconductance frequency product, and intrinsic time delay (τ), are investigated. Also, linearity parameters including VIP2, VIP3, IIP3, and the 1-dB compression point are considered. We achieve average sub-threshold swing of 14 mV for 5 decades for HD-FeTFET, and is improved by ∼ 48% and ∼ 30% for TFET and FeTFET, respectively. Moreover, the ION/IOFF ratio and the on-state current for the proposed structure are 1011 and 5.3 × 10−7 (A/μm), respectively.

8 citations

References
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Journal ArticleDOI
17 Nov 2011-Nature
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Abstract: Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

2,390 citations


"A Charge-Based Capacitance Model fo..." refers background in this paper

  • ...It has been reported that TFETs working on the band-to-band tunneling mechanism are not limited by the 60 mV/decade subthreshold swing of conventional MOSFETs and therefore, can obtain ultrahigh ON/OFF current under reduced supply voltage Vdd [1]–[4]....

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Journal ArticleDOI
TL;DR: In this paper, the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology.
Abstract: Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowest values are not based on many points. The highest current at which sub-threshold swing below 60 mV/decade is observed is in the range 1–10 nA/ \({{\mu }}\) m. A common approach to TFET characterization is proposed to facilitate future comparisons.

529 citations

Journal ArticleDOI
TL;DR: In this paper, the authors have developed models allowing a direct comparison between the single-gate, double-gate and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible.
Abstract: Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.

220 citations


"A Charge-Based Capacitance Model fo..." refers background in this paper

  • ...For simplicity, abrupt doping profiles are adopted and quantum confinement effect is ignored, which is significant and should be considered for TSi ≤ 3 nm [26]....

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Journal ArticleDOI
TL;DR: In this paper, a numerical simulation study of gate capacitance components in a tunneling field effect transistor (TFET) was performed, showing key differences in the partitioning of gate capacitor between the source and drain as compared with a MOSFET.
Abstract: We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.

201 citations

Journal ArticleDOI
TL;DR: In this paper, an analytical model for a p-n-p-n tunnel field effect transistor (TFET) working as a biosensor for label-free biomolecule detection purposes is developed and verified with device simulation results.
Abstract: In this paper, an analytical model for a p-n-p-n tunnel field-effect transistor (TFET) working as a biosensor for label-free biomolecule detection purposes is developed and verified with device simulation results. The model provides a generalized solution for the device electrostatics and electrical characteristics of the p-n-p-n-TFET-based sensor and also incorporates the two important properties possessed by a biomolecule, i.e., its dielectric constant and charge. Furthermore, the sensitivity of the TFET-based biosensor has been compared with that of a conventional FET-based counterpart in terms of threshold voltage (Vth) shift, variation in the on-current (Ion) level, and Ion/Ioff ratio. It has been shown that the TFET-based sensor shows a large deviation in the current level, and thus, change in Ion can also be considered as a suitable sensing parameter. Moreover, the impacts of device parameters (channel thickness and cavity length), process variability, and process-induced damage on the sensitivity of the biosensor have also been discussed.

147 citations