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A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS

TL;DR: This paper presents a detailed design of an innovative discrete-time charge-sharing bandpass filter with a feedback technique for boosting its quality factor and the resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden.
Abstract: This paper presents a detailed design of an innovative discrete-time charge-sharing bandpass filter with a feedback technique for boosting its quality factor. The design is implemented in 40-nm bulk CMOS, and it was integrated in silicon as part of a complete super-heterodyne receiver. In the proposed topology, cross-connected transconductors are used to boost the quality factor. The resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden. The passive filter is fully programmable, which allows for an intermediate frequency selection in the range of 20 MHz to 100 MHz. The consequent variable bandwidth enables its use for either narrowband or wideband applications. The passive filter, with transconductance amplification and clock generation, occupies an area of $0.24 \times 0.28\ \mathbf{mm}^{2}$ with a power consumption of 8 mW when operating with a 500 MHz sampling frequency.

Summary (2 min read)

Introduction

  • Nevertheless, complex strategies were sometimes required to overcome the typical issues of 2nd order non-linearity, flicker noise and DC offsets [1]–[3].
  • The introduction of N-path filters in the RF front-end led the way to the start of this new revived interest in super-heterodyne receivers [4].
  • The main drawback presented by this solution are the filter replicas at the sampling rate as a consequence of the discrete-time (DT) nature of the filter, which are then folded back to the band of interest.
  • Its main advantages over the traditional CS-BPF approach are discussed, and the small noise impact of the circuit modification is carefully analysed.

II. CHARGE-SHARING BANDPASS FILTER

  • The basic charge-sharing bandpass filter (CS-BPF) is synthesized from the 4th-order Infinite Impulse Response (IIR) lowpass filter (LPF) [7].
  • To include these variations, a more general CS-BPF transfer function is given by (2).
  • In comparison to the 4/4-phase CS-BPF, the 8/8- phase CS-BPF has a better filtering characteristic but the attenuation far from the central frequency is limited.

III. MODIFIED CHARGE-SHARING BANDPASS FILTER

  • Even though both methodologies are very effective to increase the Q-factor of the CS-BPF, they also increase the overall number of switches, the number of clock buffers, and consequently the power consumption.
  • Hence, each of the clock generation circuits is going to consume 2x more power.
  • Secondly, as the order of the CS-BPF increases, a secondary peak appears.
  • Based on these points, the authors conclude that increasing the order of the filter beyond two (e.g., 4/8-phase BPF) is hardly worth the cost of complexity and power consumption.
  • Fig. 4 shows the schematic of a 4/8 CS-BPF modified using this negative impedance.

B. Noise analysis of the modified charge-sharing bandpass filter

  • Based on the noise analysis of the 4/4-phase CS-BPF presented in [7], the noise contribution of the modified 4/8-phase CS-BPF is presented hereafter.
  • Hence, after taking the folding into consideration, the sampled noise PSD of the switch and the inverter are given by (9) and (10), respectively [13].
  • The purpose of this analysis is to compare the noise of the 4/8-phase CS-BPF with and without the addition of the negative impedance.
  • The noise sources are uncorrelated, so superposition can be used to compute the contribution of each source to the output noise.
  • Fig. 7 shows the output noise of the filter with and without the negative impedance.

IV. CIRCUIT IMPLEMENTATION

  • The modified 4/8-phase CS-BPF was implemented and measured as the second filtering stage of a complete receiver presented in fig. 8 [6].
  • The RF front-end is composed of wideband LNTA, 25% duty-cycle sampling mixer, 4/4 full-rate CS-BPF which operates at the mixer sampling rate, and clock generation circuits.
  • The second stage is composed of a basic ”inverter-like” transconductor (Gm-cell) stage detailed in fig.
  • The Gm-cell gives a gain of 12.8 dB when combined with the filter input resistance.
  • The eight 12.5% duty-cycle clock phases required by the filter are generated by the frequency divider-by-4 (fig. 10(a)).

V. RESULTS

  • The DT filter was implemented in silicon as part of the receiver designed and fabricated in TSMC 40-nm CMOS (fig. 11) [6].
  • The filter, the Gm-cell and the 8-phase clock generation circuit jointly occupy a slicon area of 0.24 x 0.28 mm2.
  • According to (3), the resolution of the capacitor banks allow for center frequency programming in the range of 20 MHz to 60 MHz, which creates a variable passband characteristic due to the constant quality-factor presented by their filter design.
  • As expected by the noise analysis, noise figure is not strongly impacted by the modification (fig. 13(b)).

VI. CONCLUSION

  • This paper presented a detailed analysis of a newly modified charge-sharing bandpass filter.
  • The discrete-time filter is fully-programmable, which allows for both intermediate frequency and passband adjustments.
  • This flexibility makes this technique a good candidate for narrowband and wideband RF transceiver applications.
  • The charge-sharing bandpass filter topology is modified using cross-connected transconductors at the filter inputs which enables higher selectivity without increasing complexity, noise and power consumption.
  • The filter is implemented in 40-nm bulk CMOS and it occupies an area of 0.24 x 0.28 mm2, considering the transconductor amplifier, and the clock generation circuit area altogether.

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A Charge-Sharing Bandpass Filter Topology with
Boosted Q-Factor in 40-nm CMOS
Filipe D. Baumgratz
, Sandro B. Ferreira
, Michiel Steyaert
, Sergio Bampi
, and Filip Tavernier
PGMicro, UFRGS, Porto Alegre, Brazil
Email: fdbaumgratz@inf.ufrgs.br
PPGEE / itt Chip, Unisinos University, Sao Leopoldo, Brazil
ESAT-MICAS, KU Leuven, Leuven, Belgium
Abstract—This paper presents a detailed design of an in-
novative discrete-time charge-sharing bandpass filter with a
feedback technique for boosting its quality factor. The design
is implemented in 40-nm bulk CMOS, and it was integrated in
silicon as part of a complete super-heterodyne receiver. In the
proposed topology, cross-connected transconductors are used to
boost the quality factor. The resulting selectivity of the complex
filter is equivalent to a higher order filter but without the power
consumption burden. The passive filter is fully programmable,
which allows for an intermediate frequency selection in the range
of 20 MHz to 100 MHz. The consequent variable bandwidth
enables its use for either narrowband or wideband applications.
The passive filter, with transconductance amplification and clock
generation, occupies an area of 0.24 x 0.28 mm
2
with a power
consumption of 8 mW when operating with a 500 MHz sampling
frequency.
Index Terms—charge-sharing bandpass filter, discrete-time,
noise, switched-capacitor.
I. INTRODUCTION
For many years, the basic choice of a receiver (RX) archi-
tecture has been direct conversion (DC) or a low-intermediate-
frequency (IF) at most. The main reason for this preference
has been usually the easier integration of the low-pass filters
and the lack of image in the DC implementation, or the easier
baseband filtering in the case of the low-IF implementation.
Nevertheless, complex strategies were sometimes required to
overcome the typical issues of 2
nd
order non-linearity, flicker
noise and DC offsets [1]–[3].
Recently, the super-heterodyne architecture has also become
an option with the advent of high-Q bandpass filter (BPF)
integration, avoiding the large external filters required to solve
the image proplem in the past. The introduction of N-path
filters in the RF front-end led the way to the start of this new
revived interest in super-heterodyne receivers [4]. The N-path
”complex” implementation can successively attenuate the RF
image and, most important, it benefits directly from technology
scaling, as it is implemented only with MOS switches and
capacitors, all controlled by digital full-swing clocks. The
main drawback presented by this solution are the filter replicas
at the sampling rate as a consequence of the discrete-time (DT)
nature of the filter, which are then folded back to the band of
interest. This ”replica” folding issue was solved by the full-
rate charge-sharing (CS) BPF introduced in [5]. In [6], an
enhancement to the full-rate CS-BPF was introduced, which
in turn allows for a sharper filtering without additional power
consumption burden.
In this paper, the modified CS-BPF which was tested in [6]
has its CMOS design presented in detail. Its main advantages
over the traditional CS-BPF approach are discussed, and the
small noise impact of the circuit modification is carefully
analysed. Section II reviews and generalizes the CS-BPF DT
architecture. The modified CS-BPF and the noise analysis are
presented in Section III. The filter architecture, simulation
results and receiver measurements are presented in Sections
IV and V, and the paper conclusions are drawn in Section VI.
II. CHARGE-SHARING BANDPASS FILTER
The basic charge-sharing bandpass filter (CS-BPF) is syn-
thesized from the 4
th
-order Infinite Impulse Response (IIR)
lowpass filter (LPF) [7]. To better understand this process, we
start by the well-known first order IIR LPF with current input
[8], shown in fig. 1(a). In this circuit, an input charge packet is
stored in a history capacitor (C
H
), and on phase φ
1
, partially
transferred to a previously discharged rotating capacitor (C
R
),
acting as a lossy component. The order of the IIR LPF can be
easily increased by adding more C
H
capacitors to share the
charge stored in C
R
during subsequent phases, φ
1
, φ
2
and so
forth [8]. Hence, as shown in fig. 1(b), a 4
th
-order IIR LPF is
created by sharing the charge of C
R
with three other C
H
[9].
The basic CS-BPF is created by connecting four inputs with
increasing 90-degree phase shifts, to the 4
th
-order IIR LPF, as
shown in fig. 1(c). Therefore, each C
H
stores the input charge
of a different input, which is sampled by C
R
on one phase
and shared with the next C
H
on the next phase [7]. In order
to create a full-rate 1
st
-order CS-BPF, four basic cells of the
CS-BPF are connected, as shown in fig. 1(d) [7], with the four
25% duty-cycle clocks phases in fig. 1(e). In [10], a generic
CS-BPF has been presented and named as M/N-phase CS-
BPF, where M is the number of inputs and N the number of
phases. This nomenclature will be used hereafter.
Based on the schematic of the 4/4-phase CS-BPF presented
in fig. 1(d), the transfer function is given by [7]
H(z) =
k
(1 az
1
) e
j
π
2
(1 a) z
1
, (1)
978-1-5386-7431-4/18/$31.00 © 2018 IEEE

φ
1
φ
2
C
R
C
H
v
out
q
in
(a)
φ
1
φ
2
φ
3
φ
4
φ
5
C
R
C
H
C
H
C
H
C
H
v
in
v
out
q
in
(b)
φ
1
φ
2
φ
3
φ
4
C
R
C
H
C
H
C
H
C
H
v
out,0
v
out,180
v
out,90
v
out,270
q
in,0
q
in,90
q
in,180
q
in,270
(c)
Bank 4
φ
2
φ
3
φ
4
φ
1
C
R
Bank 3
φ
3
φ
4
φ
1
φ
2
C
R
Bank 2
φ
4
φ
1
φ
2
φ
3
C
R
Bank 1
φ
1
φ
2
φ
3
φ
4
C
R
C
H
C
H
C
H
C
H
v
out,0
v
out,90
v
out,180
v
out,270
q
in,0
q
in,90
q
in,180
q
in,270
(d)
φ
1
φ
2
φ
3
φ
4
(e)
Fig. 1. (a) The 1
st
-order and (b) 4
th
order IIR LPF. (c) The CS-BPF basic
cell and (d) 1
st
-order full-rate CS-BPF. (e) The 25% clock, which drives the
4/4-phase CS-BPF filter.
where k = 1/(C
R
+ C
H
) and a = C
H
/(C
H
+ C
R
). The filter
Q-factor obtained from (1) is ideally 0.5 and can be easily
improved in two different ways: by increasing the number
of inputs (fig. 2(a)), or by adding lowpass poles (fig. 2(b)).
To include these variations, a more general CS-BPF transfer
function is given by (2).
H(z) =
k
(1 a) z
1
N/M1
(1 az
1
)
N/M
e
j
2π
M
[(1 a) z
1
]
N/M
. (2)
40 20 0 20 40
60
80
30
25
20
15
10
5
0
Frequency [MHz]
Normalized gain [dB]
BPF 4/4 BPF 8/8
BPF 16/16
(a)
40 20 0 20 40
60
80
30
25
20
15
10
5
0
Frequency [MHz]
Normalized gain [dB]
BPF 4/4 BPF 4/8
BPF 4/12 BPF 4/16
(b)
Fig. 2. (a) Filtering characteristic of 4/4-phase, 8/8-phase, and 16/16-phase
CS-BPF;(b) Filtering characteristic of 4/4-phase, 4/8-phase, 4/12-phase, and
4/16-phase CS-BPF.
Based on (2), the transfer functions of two Q-factor enhanc-
ing alternatives are presented in fig. 2(a): 8/8-phase, 16/16-
phase, and in fig. 2(b): 4/8-phase, 4/12-phase, and 4/16-phase
CS-BPF. In comparison to the 4/4-phase CS-BPF, the 8/8-
phase CS-BPF has a better filtering characteristic but the
attenuation far from the central frequency is limited. This
limitation is not presented by higher order filters like the 4/8,
4/12, and so forth, which can provide strong attenuation both
close and far from the central frequency (fig. 2(b)). The basic
cell implementations of the 8/8-phase and the 4/8-phase CS-
BPF alternatives are presented in fig. 3(a) [10] and fig. 3(b)
[11]. To obtain the full-rate equivalents, 8 C
R
s are placed in
parallel, in a similar fashion to fig. 1(d).
φ
1
φ
2
φ
3
φ
4
φ
5
φ
6
φ
7
φ
8
C
R
C
H
C
H
C
H
C
H
C
H
C
H
C
H
C
H
v
out,0
v
out,90
v
out,180
v
out,270
v
out,45
v
out,135
v
out,225
v
out,315
q
in,0
q
in,45
q
in,90
q
in,135
q
in,180
q
in,225
q
in,270
q
in,315
(a)
φ
1
φ
2
φ
3
φ
4
φ
5
φ
6
φ
7
φ
8
C
R
C
H
C
H
C
H
C
H
C
H
C
H
C
H
C
H
v
in,0
v
in,90
v
in,180
v
in,270
v
out,0
v
out,90
v
out,180
v
out,270
q
in,0
q
in,90
q
in,180
q
in,270
(b)
Fig. 3. (a) The schematic of a 8/8-phase CS-BPF and (b) a 4/8-phase CS-BPF.
Regardless of the number of inputs and the order, the central
frequency of the CS-BPF is solely controlled by the ratio of
the capacitors C
H
and C
R
. This is the main advantage of the
CS-BPF over the other bandpass filters since the capacitors
in modern CMOS technologies are very robust to mismatch
which plagues traditional topologies based on Gm-C, active-
RC, or biquad. The CS-BPF central frequency is given by [10]
f
c
=
f
s
2π
arctan
(1 a)sin(2π/N)
a + (1 a)cos(2π/N)
. (3)
III. MODIFIED CHARGE-SHARING BANDPASS FILTER
Even though both methodologies are very effective to in-
crease the Q-factor of the CS-BPF, they also increase the
overall number of switches, the number of clock buffers, and
consequently the power consumption. For instance, consid-
ering only the number of switches, the power consumption
of the 4/8-phase BPF is 4x higher than the 4/4-phase BPF.
Also, the switches of the 4/8-phase BPF work at a 2x-higher
sampling rate. Hence, each of the clock generation circuits
is going to consume 2x more power. Additionally, two other
issues might arise from the increase of the filter order and
the number of inputs. Firstly, in both cases, the sampling
frequency of the CS-BPF increases. Hence, the switches must
be proportionally faster, or the filter performance will decrease.
Secondly, as the order of the CS-BPF increases, a secondary
peak appears. This second peak is barely noticeable on the
4/8-phase CS-BPF transfer function (TF), but it already affects
the symmetry of the magnitude TF. Due to the second peak,
the image attenuation improves only by 5 dB from the 4/8-
phase to the 4/16-phase BPF [6]. Based on these points, we
conclude that increasing the order of the filter beyond two
(e.g., 4/8-phase BPF) is hardly worth the cost of complexity
and power consumption.
Another possibility to enhance the Q-factor is by adding a
pair of cross-connected transconductors at both the in-phase
(I) and quadrature (Q) inputs of the filter. In fact, this cross-
connected topology works as a negative impedance. Fig. 4
shows the schematic of a 4/8 CS-BPF modified using this

negative impedance. By improving the Q-factor, both the
image attenuation and the filtering of out-of-band blockers
are improved. Nevertheless, since the I and Q paths are still
independent, the I/Q mismatch remains affected mainly by the
clock generation [6], [12].
Fig. 4. Modified 4/8 phase CS BPF Schematics.
A. Implementation of the modified 4/8-phase CS-BPF
The negative impedance was implemented with inverters as
presented in fig. 4. Based on this schematic, the time-domain
input and output voltages of the modified 4/8-phase BPF at
t = nT
S
are respectively
v
in,i
[n] = av
in,i
[n 1] + (1 a)v
out,i90
[n 1]
+ kq
i
[n] + β(1 a)v
in,i180
[n], (4)
v
out,i
[n] = av
out,i
[n 1] + (1 a)v
in,i
[n 1], (5)
where i {0
, 90
, 180
, 270
} and represents the phase of
the input or output, and β is the gain of the feedback loop
used to implement the negative impedance. By converting (4)
and (5) from the time-domain to the z-domain, the transfer
function below is obtained.
H(z) =
k (1 a) z
1
(1 az
1
)
2
1 +
1a
1az
1
β
j (1 a)
2
z
2
, (6)
Fig. 5(a) shows the plotted transfer function of the modified
4/8-phase CS-BPF. By setting β to -0.5, according to the
figure, an attenuation higher than 35 dB at the image frequency
would be obtained, which is even better than the 4/16-phase
CS-BPF case. However, |β| < 0.5 should be adopted to ensure
stability [6], and the CS-BPF would operate close to the
oscillation condition. Fig. 5(b) presents a zoomed version of
the pole representation of (6) as β is varied, showing that one
of the poles is crossing the unit circle at β = 0.5.
40 20 0 20 40
60
80
40
30
20
10
0
Frequency [MHz]
Normalized gain [dB]
β
= 0
β
= -0.1
β
= -0.2
β
= -0.3
β
= -0.35
β
= -0.4
β
= -0.45
β
= -0.5
(a)
0.92 0.94
0.96
0.98 1.00 1.02
0.04
0.02
0.00
0.02
0.04
0
β
0.5
Real Axis
Imaginary Axis
β
= 0
β
= 0.1
β
= 0.2
β
= 0.3
β
= 0.4
β
= 0.5
(b)
Fig. 5. (a) Modified 4/8-phase CS BPF transfer function;(b) Pole-zero
mapping of the modified 4/8-phase CS BPF TF (6).
B. Noise analysis of the modified charge-sharing bandpass
filter
In addition to stability, noise is a concern when the negative
impedance is added to the filter. Based on the noise analysis of
the 4/4-phase CS-BPF presented in [7], the noise contribution
of the modified 4/8-phase CS-BPF is presented hereafter.
The noise sources of the filter are the switches and the
inverters of the negative impedance, with thermal noise power
spectral density (PSD) given, respectively, by (7) and (8).
S
sw
(f) = 4kT R
ON
(7)
S
inv
(f) = 4kT γ/G
m
, (8)
where k is the Boltzmann constant, T is the absolute tempera-
ture, R
ON
is the resistance when the switch is closed, γ is the
noise parameter, and G
m
is the overall transconductance of
the inverter. However, due to the sampling process, the noise
from frequencies above f
s
/2 is folded to the interval 0-to-
f
s
/2. Hence, after taking the folding into consideration, the
sampled noise PSD of the switch and the inverter are given
by (9) and (10), respectively [13].
S
sw,S/H
(f) =
2kT
C
R
f
s
, 0 f f
s
/2 (9)
S
inv ,S/H
(f) =
2kTγ
G
m
C
R
f
s
R
ON
. 0 f f
s
/2 (10)
The sampled noise PSDs will be considered as the noise
sources in the following analysis.
Fig. 6 shows the simplified noise model, which considers
no input charge packets. The purpose of this analysis is
to compare the noise of the 4/8-phase CS-BPF with and
without the addition of the negative impedance. First, the noise
contribution of each noise source to each output is calculated.
In fact, since the circuit is symmetrical, the noise at all outputs
are equal, and we need to only compute for one output.
The noise sources are uncorrelated, so superposition can be
used to compute the contribution of each source to the output
noise. Therefore, to calculate the output noise due to v
n1
, the
other noise sources are set to zero. The time-domain noise of
the first output and input at t = nT
s
is given by
v
out,0
[n] = av
out,0
[n 1] + bv
in,0
[n 1] bv
n1
[n 1],
(11)

φ
1
V
2
n1
V
2
n2
φ
2
φ
5
V
2
n5
V
2
n6
φ
6
φ
3
V
2
n3
V
2
n4
φ
4
φ
7
V
2
n7
V
2
n8
φ
8
C
R
C
H
C
H
C
H
C
H
C
H
C
H
C
H
C
H
V
2
n9
V
2
n10
v
in,0
v
in,180
V
2
n11
V
2
n12
v
in,90
v
in,270
v
out,0
v
out,180
v
out,90
v
out,270
Fig. 6. Noise sources of the modified 4/8-phase CS-BPF.
v
in,0
[n] = av
in,0
[n 1] + bv
out,270
[n 1]
+ βbv
in,180
[n] + bv
n1
[n], (12)
where b = 1 a, and v
n1
=
q
V
2
n1
. The time-domain noise
equations of the other three inputs and outputs are
v
out,i
[n] = av
out,i
[n 1] + bv
in,i
[n 1], (13)
v
in,i
[n] = av
in,i
[n 1] + bv
out,i90
[n 1]
+ βbv
in,i180
[n], (14)
where i {90
, 180
, 270
}. By converting (11) - (14) from
the time-domain to the z-domain, the noise transfer function
of v
n1
to each output is
H
1
=
1 az
1
7
bz
1
1 az
1
6
b
2
z
1
+ A
1
(1 az
1
)
8
+ b
8
z
8
+ B
1
, (15)
H
2
=
1 az
1
5
b
3
z
3
1 az
1
4
b
4
z
3
+ A
2
(1 az
1
)
8
+ b
8
z
8
+ B
1
, (16)
H
3
=
1 az
1
3
b
5
z
5
1 az
1
2
b
6
z
5
+ A
3
(1 az
1
)
8
+ b
8
z
8
+ B
1
, (17)
H
4
=
1 az
1
b
7
z
7
b
8
z
7
+ A
4
(1 az
1
)
8
+ b
8
z
8
+ B
1
, (18)
where H
1
, H
2
, H
3
, and H
4
are the noise TFs to v
out,0
,
v
out,90
, v
out,180
, and v
out,270
, respectively. Also, the terms
A
1
, A
2
, A
3
, A
4
, and B
1
are introduced by the negative
impedance and presented below:
A
1
=
2
1 az
1
+ b
h
1 az
1
4
b
3
β
2
z
1
+
1 az
1
b
6
βz
5
+
1 az
1
3
b
5
β
4
z
1
, (19)
A
2
=
1 az
1
3
b
5
β
2
z
3
1 az
1
2
b
6
β
2
z
3
b
8
βz
7
, (20)
A
3
=
1 az
1
5
b
3
βz
1
+
1 az
1
3
b
5
β
3
z
1
+
1 az
1
b
7
β
2
z
5
, (21)
A
4
=
h
1 az
1
2
2
1 az
1
b β
2
b
2
i
1 az
1
2
βb
4
z
3
, (22)
B
1
= 2
1 az
1
6
b
2
β
2
1 az
1
4
b
4
β
4
+ 4
1 az
1
3
b
5
βz
4
. (23)
Hence, if these terms are considered zero, we have the noise
TF of the original 4/8-phase CS-BPF.
Since the filter is symmetrical, the TFs (15) - (18) are the
same for the sources
V
2
n1
, V
2
n3
, V
2
n5
, and V
2
n7
. They will also be
the same for the noise sources V
2
n2
, V
2
n4
, V
2
n6
, and V
2
n8
, but with
an opposite sign. Finally, repeating the previous methodology,
the noise transfer function of v
n9
(i.e. one inverter of the
negative impedance) to each output is
H
5
=
1 az
1
6
b
2
z
1
+ A
5
(1 az
1
)
8
b
8
z
8
+ B
2
, (24)
H
6
=
1 az
1
4
b
4
z
3
+
1 az
1
2
b
6
β
2
z
3
(1 az
1
)
8
b
8
z
8
+ B
2
, (25)
H
7
=
1 az
1
2
b
6
z
5
+ A
6
(1 az
1
)
8
b
8
z
8
+ B
2
, (26)
H
8
=
2
1 az
1
3
βb
5
z
3
+ b
8
z
7
(1 az
1
)
8
b
8
z
8
+ B
2
. (27)
where the terms A
5
, A
6
, and B
2
are
A
5
=
1 az
1
4
β
2
b
4
z
1
1 az
1
βb
7
z
5
, (28)
A
6
= β
1 az
1
5
b
3
z
1
β
3
1 az
1
3
b
5
z
1
, (29)
B
2
=
h
2
1 az
1
3
β +
1 az
1
b
2
β
3
4b
3
z
4
i
×
1 az
1
3
βb
2
. (30)
Similary to (15) - (18), the TFs (24) - (27) are the same for
the sources V
2
n9
, V
2
n10
, V
2
n11
, and V
2
n12
because the filter is
symmetrical.
The differential discrete-time output noise is composed by
noise components of all these sources as shown below:
V
2
on
= (H
1
H
3
)
2
V
2
n1
+ (H
4
H
2
)
2
V
2
n3
+ (H
3
H
1
)
2
V
2
n5
+ (H
2
H
4
)
2
V
2
n7
+ (H
3
H
1
)
2
V
2
n2
+ (H
2
H
4
)
2
V
2
n4
+ (H
1
H
2
)
2
V
2
n6
+ (H
4
H
2
)
2
V
2
n8
+ (H
5
H
7
)
2
V
2
n9
+ (H
8
H
6
)
2
V
2
n10
+ (H
7
H
5
)
2
V
2
n11
+ (H
6
H
8
)
2
V
2
n12
. (31)
Since the 8 switches are equal and the 4 inverters are also
equal, the previous equation can be further simplified to
V
2
on
= 4
(H
1
H
3
)
2
+ (H
4
H
2
)
2
V
2
n1
+ 2
(H
5
H
7
)
2
+ (H
5
H
7
)
2
V
2
n9
. (32)
After that, by plotting (32) and the V
2
on
of the original 4/8-
phase CS-BPF, we can evaluate how the negative impedance
affects the noise of the filter. In order to perform this compar-
ison, a 4/8-phase CS-BPF with C
R
= 4 pF, C
H
= 19 pF, and
f
s
= 1 GHz, and a negative impedance with β = 0.2 are
considered. Fig. 7 shows the output noise of the filter with and
without the negative impedance. Additionally, the dashed and
dashed-dotted lines show the composition of the filter output
noise with negative impedance, i.e., the noise contribution

of the switches and inverters. Since the negative impedance
enhances the gain of the filter, a slight reduction of the noise
is observed, and a small impact in the overall RX noise figure
is expected.
0 10 20 30 40
50 60
70 80
10
21
10
20
10
19
10
18
10
17
Frequency [MHz]
Output noise power [V
2
/Hz]
V
2
no,4/8 BPF
V
2
no,new 4/8 BPF
V
2
no,sw
V
2
no,inv
Fig. 7. The output noise PSD calculation of the 4/8-phase BPF with and
without negative impedance are presented with solid lines. Dashed and dashed-
dotted lines show the output noise of the switches and inverters of the modified
4/8-phase BPF.
IV. CIRCUIT IMPLEMENTATION
The modified 4/8-phase CS-BPF was implemented and
measured as the second filtering stage of a complete receiver
presented in fig. 8 [6].
LNTA
BPF 1
GM
GM
+
BPF 2
I
Q
Buffer
i
RF
i
BB,I
i
BB,Q
25%LO
25%LO 12.5%LO
2
f
RF
Z
in,MX
Z
BB
f
IF
Z
BB
Fig. 8. Simplified block diagram of the complete implemented receiver.
The receiver in fig. 8 is composed of two basic stages: a
RF front-end and a intermediate frequency (IF) filtering stage.
The RF front-end is composed of wideband LNTA, 25%
duty-cycle sampling mixer, 4/4 full-rate CS-BPF which oper-
ates at the mixer sampling rate, and clock generation circuits.
The front-end is a super-heterodyne architecture covering the
frequency range from 500 MHz to 4 GHz, with variable
intermediate frequency (IF) and adjustable channel pass-band.
It is mainly in charge of low-noise amplification and out-of-
band filtering, and was presented in detail in [6].
The second stage is composed of a basic ”inverter-like”
transconductor (Gm-cell) stage detailed in fig. 9 and a modi-
fied 4/8-phase CS-BPF (fig. 4) operating at a fixed 500-MHz
sampling rate. The Gm-cell gives a gain of 12.8 dB when
combined with the filter input resistance.
The eight 12.5% duty-cycle clock phases required by the
filter are generated by the frequency divider-by-4 (fig. 10(a)).
The latches presented in fig. 10(b) are implemented using tri-
state inverters (fig. 10(c)) in order to achieve sharp transitions.
V. RESULTS
The DT filter was implemented in silicon as part of the
receiver designed and fabricated in TSMC 40-nm CMOS
CMFB
V
CMFB
R
B
V
CMFB
R
B
V
CMFB
C
B
C
B
R
B
V
B6
R
B
V
B6
C
B
C
B
v
in+
v
in
+
v
out
0.9 V 0.9 V
16µm
240nm
20µm
240nm
v
out+
v
out
V
CM
V
CMFB
CMFB
Fig. 9. ”Inverter-like” transconductor.
D
D Q
Q
CLK
CLK
Latch 1
D
D Q
Q
CLK
CLK
Latch 2
D
D Q
Q
CLK
CLK
Latch 3
D
D Q
Q
CLK
CLK
Latch 4
CLK
CLK
(a)
CLK
CLK
CLK
CLK
D
D
Q
Q
(b)
IN
OUT
0.9 V
CLK
CLK
(c)
Fig. 10. (a) The divider-by-4 that generates the 12.5% non-overlaping clock,
(b) the tristate latchs, and (c) the tristate circuit.
(fig. 11) [6]. The filter, the Gm-cell and the 8-phase clock
generation circuit jointly occupy a slicon area of 0.24 x 0.28
mm
2
.
0.9 mm
1.3 mm
LNTA
Mixer
BPF 4/4
4-Phase CLK
GM-cells
BPF 4/8
8-Phase CLK
Buffers
Fig. 11. Chip micrograph.
The filter implementation is detailed in fig. 4. The feedback
gain β is implemented as G
m
x R
in
, where G
m
is the inverter
transcondutance, and R
in
is the input resistance of the filter,
R
in
1/f
s
C
R
. C
H
and C
R
are implemented using 8-bit
binary-programmed capacitor banks, ranging from 600 fF
to 9 pF and 25 fF to 375 fF, respectively. According to
(3), the resolution of the capacitor banks allow for center
frequency programming in the range of 20 MHz to 60
MHz, which creates a variable passband characteristic due
to the constant quality-factor presented by our filter design.
Consequently, the filter is suitable for both wideband and
narrowband applications. For instance, the 20 MHz bandwidth
required by 791 - 821 MHz and 3600 - 3800 MHz LTE bands
can be easily achieved by moving the IF to -40 MHz as shown
in the extracted simulations (fig. 12).
Fig. 13(a) shows the improvement in selectivity of the
β = 0.2 modified filter vs the traditional 4/8-phase CS-BPF
approach. The feedback is used here to compensate for losses

Citations
More filters
Journal ArticleDOI
TL;DR: The proposed strategy, cross-connected transconductors are used to boost the quality factor of discrete-time charge-sharing bandpass filters and the resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden.
Abstract: This paper presents a detailed design of an innovative feedback technique for boosting quality factor of discrete-time charge-sharing bandpass filters. The technique is verified in a 40-nm bulk CMOS implementation. The design was integrated in silicon as part of a complete super-heterodyne receiver. In the proposed strategy, cross-connected transconductors are used to boost the quality factor. The resulting selectivity of the complex filter is equivalent to a higher order filter but without the power consumption burden. The passive filter is fully programmable, which allows for an intermediate frequency selection in the range of 20–100 MHz. The consequent variable bandwidth enables its use for either narrowband or wideband applications. The passive filter, with transconductance amplification and clock generation, occupies an area of $$0.24 \times 0.28~{\text{mm}}^{2}$$ with a power consumption of 8 mW when operating with a 500 MHz sampling frequency.

1 citations

References
More filters
Book
01 Jan 1986
TL;DR: In this article, the authors present an overview of the non-ideal effects in Switched-Capacitor Circuits, as well as their application in switch-capacitor circuits.
Abstract: Transformation Methods. MOS Devices as Circuit Elements. MOS Operational Amplifiers. Switched-Capacitor Filters. Nonfiltering Applications of Switched-Capacitor Circuits. Nonideal Effects in Switched-Capacitor Circuits. Systems Considerations and Applications. Index.

923 citations

Journal ArticleDOI
A.S. Sedra1
01 Nov 1987
TL;DR: That's it, a book to wait for in this month; even you have wanted for long time for releasing this book analog mos integrated circuits for signal processing; you may not be able to get in some stress, but now, the authors are coming to give you excellent solution.
Abstract: That's it, a book to wait for in this month. Even you have wanted for long time for releasing this book analog mos integrated circuits for signal processing; you may not be able to get in some stress. Should you go around and seek fro the book until you really get it? Are you sure? Are you that free? This condition will force you to always end up to get a book. But now, we are coming to give you excellent solution.

344 citations


"A Charge-Sharing Bandpass Filter To..." refers methods in this paper

  • ...Hence, after taking the folding into consideration, the sampled noise PSD of the switch and the inverter are given by (9) and (10), respectively [13]....

    [...]

Journal ArticleDOI
TL;DR: A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna thanks to a 2.5 V linear LNA and mixer-based RF blocker filter.
Abstract: A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

176 citations

Journal ArticleDOI
TL;DR: An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters.
Abstract: We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F2 digital power amplifier (PA), featuring high efficiency. Low 1/ $f$ DCO noise allows the ADPLL to shut down after acquiring lock. The receiver operates in discrete time at high sampling rate (~10 Gsamples/s) with intermediate frequency placed beyond 1/ $f$ noise corner of MOS devices. New multistage multirate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise, and low power consumption. An integrated on-chip matching network serves to both PA and low-noise transconductance amplifier, thus allowing a 1-pin direct antenna connection with no external band-selection filters. The TRX consumes 2.75 mW on the RX side and 3.7 mW on the TX side when delivering 0 dBm in BLE.

91 citations


Additional excerpts

  • ...3(b) [11]....

    [...]

Journal ArticleDOI
TL;DR: A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz, which ensures high out-of-band linearity and compliance with LTE and future standards.
Abstract: A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm 2 , 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW.

82 citations

Frequently Asked Questions (18)
Q1. What have the authors contributed in "A charge-sharing bandpass filter topology with boosted q-factor in 40-nm cmos" ?

This paper presents a detailed design of an innovative discrete-time charge-sharing bandpass filter with a feedback technique for boosting its quality factor. 

Since the negative impedance enhances the gain of the filter, a slight reduction of the noise is observed, and a small impact in the overall RX noise figure is expected. 

The filter is implemented in 40-nm bulk CMOS and it occupies an area of 0.24 x 0.28 mm2, considering the transconductor amplifier, and the clock generation circuit area altogether. 

By converting (11) - (14) from the time-domain to the z-domain, the noise transfer function of vn1 to each output isH1 =( 1− az−1 )7 bz−1 − ( 1− az−1 )6 b2z−1 +A1− (1− az−1)8 + b8z−8 +B1 , (15)H2 =( 1− az−1 )5 b3z−3 − ( 1− az−1 )4 b4z−3 +A2− (1− az−1)8 + b8z−8 +B1 , (16)H3 =( 1− az−1 )3 b5z−5 − ( 1− az−1 )2 b6z−5 +A3− (1− az−1)8 + b8z−8 +B1 , (17)H4 =( 1− az−1 ) b7z−7 − b8z−7 +A4− (1− az−1)8 + b8z−8 +B1 , (18)where H1, H2, H3, and H4 are the noise TFs to vout,0◦ , vout,90◦ , vout,180◦ , and vout,270◦ , respectively. 

In this circuit, an input charge packet is stored in a history capacitor (CH ), and on phase φ1, partially transferred to a previously discharged rotating capacitor (CR), acting as a lossy component. 

4. The feedback gain β is implemented as Gm x Rin, where Gm is the inverter transcondutance, and Rin is the input resistance of the filter, Rin ≈ 1/fsCR. 

The purpose of this analysis is to compare the noise of the 4/8-phase CS-BPF with and without the addition of the negative impedance. 

The measured power consumption of the Gm-cell with 12.8 dB of gain and the clock generation circuits operating at 500 MHz are 2.7 mW and 5.35 mW respectively, from a 0.9V power supply. 

In [10], a generic CS-BPF has been presented and named as M/N-phase CSBPF, where M is the number of inputs and N the number of phases. 

In comparison to the 4/4-phase CS-BPF, the 8/8- phase CS-BPF has a better filtering characteristic but the attenuation far from the central frequency is limited. 

Another possibility to enhance the Q-factor is by adding a pair of cross-connected transconductors at both the in-phase (I) and quadrature (Q) inputs of the filter. 

the terms A1, A2, A3, A4, and B1 are introduced by the negative impedance and presented below:A1 = [ −2 ( 1− az−1 ) + b ] [( 1− az−1 )4 b3β2z−1+ ( 1− az−1 ) b6βz−5 ] + ( 1− az−1 )3 b5β4z−1, (19)A2 = − ( 1− az−1 )3 b5β2z−3− ( 1− az−1 )2 b6β2z−3 − b8βz−7, (20)A3 = − ( 1− az−1 )5 b3βz−1 + ( 1− az−1 )3 b5β3z−1+ ( 1− az−1 ) b7β2z−5, (21)A4 = − [ − ( 1− az−1 )2 − 2 (1− az−1) b− β2b2]( 1− az−1 )2 βb4z−3, (22)B1 = 2 ( 1− az−1 )6 b2β2 − ( 1− az−1 )4 b4β4+ 4 ( 1− az−1 )3 b5βz−4. (23)Hence, if these terms are considered zero, the authors have the noise TF of the original 4/8-phase CS-BPF. 

Regardless of the number of inputs and the order, the central frequency of the CS-BPF is solely controlled by the ratio of the capacitors CH and CR. 

The order of the IIR LPF can be easily increased by adding more CH capacitors to share the charge stored in CR during subsequent phases, φ1, φ2 and so forth [8]. 

H(z) = k [ (1− a) z−1 ]N/M−1 (1− az−1)N/M − ej 2πM [(1− a) z−1]N/M . (2)Based on (2), the transfer functions of two Q-factor enhancing alternatives are presented in fig. 

The time-domain noise equations of the other three inputs and outputs arevout,i[n] = avout,i[n− 1] + bvin,i[n− 1], (13)vin,i[n] = avin,i[n− 1] + bvout,i−90◦ [n− 1] + βbvin,i−180◦ [n], (14)where i ∈ {90◦, 180◦, 270◦}. 

The time-domain noise of the first output and input at t = nTs is given byvout,0◦ [n] = avout,0◦ [n− 1] + bvin,0◦ [n− 1]− bvn1[n− 1], (11)vin,0◦ [n] = avin,0◦ [n− 1] + bvout,270◦ [n− 1] + βbvin,180◦ [n] + bvn1[n], (12)where b = 1 − a, and vn1 = √ V 2n1. 

For instance, considering only the number of switches, the power consumption of the 4/8-phase BPF is 4x higher than the 4/4-phase BPF.