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Proceedings ArticleDOI

A chip and pixel qualification methodology on imaging sensors

25 Apr 2004-pp 435-439

AbstractThis paper presents a qualification methodology on imaging sensors. In addition to overall chip reliability characterization based on sensor's overall figure of merit, such as Dark Rate, Linearity, Dark Current Non-Uniformity, Fixed Pattern Noise and Photon Response Non-Uniformity, a simulation technique is proposed and used to project pixel reliability. The projected pixel reliability is directly related to imaging quality and provides additional sensor reliability information and performance control.

Topics: Image sensor (59%), Fixed-pattern noise (56%), Reliability (statistics) (55%), Pixel (53%), Figure of merit (51%)

Summary (2 min read)

INTRODUCTION

  • Imaging sensors of different varieties are widely used in commercial and scientific applications.
  • There have been extensive research efforts to enhance the performance of the CMOS APS imaging sensors by adopting more robust digital/analog circuit designs and sampling techniques, as well as more advanced imaging processing technology and semiconductor fabrication technologies [1-9].
  • On the other hand, few studies have concentrated on the reliability or qualification of the imaging sensors.
  • It is taken for granted that the reliability of the imaging sensors should be automatically guaranteed when the semiconductor process technologies fabricating the imaging devices have been qualified.
  • It should be noted that the environmental, mechanical and packaging evaluation procedures and tests are also part of the qualification plan and practice, but are not addressed herein.

EXPERIMENTAL DETAILS

  • The image sensor is photodiode-type CMOS active pixel sensor imaging system on chip, designed by Jet Propulsion Laboratory and manufactured by a standard commercial CMOS production line.
  • Schematic of the photodiode-type active pixel sensor cell.
  • The image sensors were stressed in parallel and stopped in a pre-set time interval to be monitored one by one for Dark Rate, Linearity, Dark Current Non-Uniformity (DCNU), Fixed Pattern Noise (FPN) and Photon Response Non-Uniformity (PRNU).
  • At the same time, the highest stress voltage at each stress temperature should be within the range when the sensor is still framing and functional.
  • During the accelerated testing, the sensors were running at 5 MHz with the clock pulse matching the stress voltage applied on the chips.

CHIP RELIABILITY PROJECTION

  • For overall VIDI APS chip reliability, Linearity and Dark Rate are the two parameters to be considered since they reflect the overall parametric shift or change on the imaging chips.
  • The characteristics trend is representative for all imaging chips under all stress conditions.
  • The percentage of the slope change of the linearity curves in Figure 4 is plotted in Figure 5, showing almost linear increasing Linearity slope versus stress time in a log-log scale.
  • Assuming the Arrhenius model [12] o a o kT E V eet β~% where t% is the chip life time at certain failure fraction and is determined to be 0.1% in their case; β, Vo, Ea, k and To are the voltage acceleration factor, operating voltage, activation energy, Boltzmann’s constant and operating temperature in Kelvin, respectively.
  • Life and failure rate can be also generated by using a percentage degradation of Dark Rate as well.

PIXEL RELIABILITY PROJECTION

  • Therefore, pixel reliability needs to be considered and projected as well.
  • The hot pixel generation rate is slow at the accelerated stress levels.
  • The pixel distributions for DCNU, FPN and PRNU did not have significant shift during their accelerated testing.
  • This happened during radiation testing when the imager failed in a sudden owing to the periphery circuit failure.
  • Acceptable image quality can be chosen based on the same experimental data or simulation results using small degradation percentage increases.

SUMMARY

  • While a reliability projection based on the imaging sensor’s overall parametric performance may provide some insight on the imager performance degradation, pixel reliability projection, either by experimental or by predicted pixel distributions, has to be performed.
  • The projected pixel reliability can be directly related to imaging quality and provide additional sensor performance information.

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A Chip and Pixel Qualification Methodology on Imaging Sensors
Yuan Chen, Steven M. Guertin, Mihail Petkov, Duc N. Nguyen, Frank Novak
2
Jet Propulsion Laboratory, California Institute of Technology , 4800 Oak Grove Drive, MS 303-230, Pasadena, CA 91109
2
NASA Langley Research Center, MS 468, 5 North Dryden St., Hampton, Virginia 23681
Phone: 818-393-0940; Fax: 818-393-4559; E-mail: yuan.chen@jpl.nasa.gov
ABSTRACT
This paper presents a qualification methodology on
imaging sensors. In addition to overall chip reliability
characterization based on sensor’s overall figure of merit, such as
Dark Rate, Linearity, Dark Current Non-Uniformity, Fixed Pattern
Noise and Photon Response Non-Uniformity, a simulation technique
is proposed and used to project pixel reliability. The projected pixel
reliability is directly related to imaging quality and provides
additional sensor reliability information and performance control.
[Keywords: CMOS Active Pixel Sensors, PD-APS, Imaging Sensor
Reliability, Pixel Reliability.]
INTRODUCTION
Imaging sensors of different varieties are widely used in
commercial and scientific applications. Compared to charge-coupled
device (CCD) image sensors, CMOS active pixel sensor (APS)
imagers are fabricated in standard CMOS processes, which make it
possible to integrate the timing and control electronics, sensor array,
signal processing electronics, analog-to-digital converter (ADC) and
full digital interface on one chip. This helps to achieve a cost-
effective highly integrated and highly compact imaging system, i.e.
camera-on-a-chip, by utilizing the same design techniques that have
been developed over the years for low-power CMOS digital and
analog circuits.
There have been extensive research efforts to enhance the
performance of the CMOS APS imaging sensors by adopting more
robust digital/analog circuit designs and sampling techniques, as
well as more advanced imaging processing technology and
semiconductor fabrication technologies [1-9].
On the other hand, few studies have concentrated on the
reliability or qualification of the imaging sensors. It is taken for
granted that the reliability of the imaging sensors should be
automatically guaranteed when the semiconductor process
technologies fabricating the imaging devices have been qualified.
However, unlike memory chips where failed bits can be detected by
functional testing and can be easily recognized as bad bits, pixels of
the imaging sensors can either be uniformly degraded or become
hot pixels. In both cases, imaging problems or decreased imaging
quality will result.
In the effort of qualifying a photodiode-type (PD) CMOS
APS imaging device for one of our space mission applications, we
developed a qualification procedure and reliability analysis approach
for imaging sensors. It should be noted that the environmental,
mechanical and packaging evaluation procedures and tests are also
part of the qualification plan and practice, but are not addressed
herein. In addition, the impact of radiation on the imagers -
including Gamma, protons and heavy ions - were presented in [10].
In this paper, a qualification methodology on imaging
sensors is presented. The experimental details of the accelerated life
testing will be described first, along with the reliability
characterizations on the imaging sensors. Then, the projection for
overall chip reliability and a simulation approach to correlate pixel
reliability and image quality will be presented, followed by
summary.
EXPERIMENTAL DETAILS
The image sensor is photodiode-type CMOS active pixel
sensor imaging system on chip, designed by Jet Propulsion
Laboratory and manufactured by a standard commercial CMOS
production line. The imager is a 512 by 512 photodiode pixel array,
which can randomly access any window in the array from 1 pixel by
1 pixel all the way to 512 pixels by 512 pixels in any rectangular
shape. The minimum interface consists of five wires: Vdd, Ground,
Serial Data Input, Serial Data Output and Clock. The imager size is
approximately 10 mm by 15.5 mm with pixel size of 12 um by 12
um. The nominal power supply Vdd is 3.3V.
Figure 1 gives a schematic of the photodiode-type active
pixel sensor cell [1, 3-4, 11]. In the pixel sensor cell, the transistors
designed for the imagers in our study have a minimum channel
length of 0.5um.
Vdd
row sel
M1
M2
M3 col sel
Figure 1. Schematic of the photodiode-type active pixel sensor cell.
Light into the photo-diode generates a small current
proportional to the light intensity and photo-diode area. Due to this
small photo current, the nMOS transistor (M1) operates in weak
inversion. In this region, the gate to source voltage depends
logarithmically on the drain current with a constant slope
independent of the technology and equal to kT/q, as shown in the
following simplified expression for the gate-source voltage for a
transistor working in its weak inversion region [3-4,11]:
th
d
d
gs
V
I
I
W
L
q
kT
V += )ln(
0
where V
gs
is the gate-source voltage, I
d
is the drain current or the
photo current, I
d0
is the I
d
at the on-set of weak inversion, W and L
are the width and length of the channel of the transistor, T is the
temperature in Kelvin and k is the Bolzmann constant. Therefore,
the pixel structure yields a continuous signal that is proportional to
the instantaneous light intensity.
Because of the characteristic deviation of the active
transistor M1 in the pixel cell, non-uniformity among pixels is

expected. Therefore, the following parameters are some important
figures of merit for imaging sensors.
Fixed pattern noise (FPN) is the variation from pixel to
pixel when the imager operated as normal with no light input. The
FPN is typically measured using the full array. Photon Response
Non-Uniformity (PRNU) is the gain difference between pixels and it
is typically taken with a field at approximately 50% of full well.
Dark Current is the thermally generated electrons discharging the
pixel just as if a photon had hit the pixel. Dark Current Non-
Uniformity (DCNU) is the leakage difference between pixels with a
dark field over a long integration time. All these parameters are
functions of temperature and measured during the accelerated
testing. Also, Dark Rate and Linearity, defined as the mV/s from
Dark Current and PRNU measurements, respectively, were also
monitored.
Shown in Figure 2, the accelerated testing was fully
controlled by LabView software running on a personal computer.
The image sensors were stressed in parallel and stopped in a pre-set
time interval to be monitored one by one for Dark Rate, Linearity,
Dark Current Non-Uniformity (DCNU), Fixed Pattern Noise (FPN)
and Photon Response Non-Uniformity (PRNU).
Figure 2. Schematic of the accelerated testing set-up.
The accelerated testing was performed on the image
sensors at elevated bias and temperature levels to accelerate
thermally activated failure mechanisms. It is very important to
ensure that the highest stress temperature cannot exceed the glass
transition temperature for the die attach material of the packages, in
our case, 117°C. At the same time, the highest stress voltage at each
stress temperature should be within the range when the sensor is still
framing and functional. The highest voltage that can be applied on
the imager when it is still framing was simulated as 6.8V, later
confirmed by experiment.
Following this procedure, the stress conditions were
determined as 6.5V at 85°C, 6.5V at 45°C, and 6.0V at 85°C to
estimate voltage acceleration factor and activation energy. The total
testing sample size was 18 with 5~6 imager sensors for each
accelerated stress condition. The limited number of stress conditions
in our case results from cost constraints. Additional stress conditions
and more testing samples can be utilized to further refine the bias
and temperature acceleration factors. Figure 3 gives the stress
condition matrix with the mission operating condition and the
recommended additional stress conditions.
3
3.5
4
4.5
5
5.5
6
6.5
7
-40 -20 0 20 40 60 80 100
Temperature (C)
Bias (V)
Stress Conditions Used
MIssion Operating Condition
Recommended Additional Stress Conditions
Figure 3. Stress matrix for the accelerated testing.
During the accelerated testing, the sensors were running at
5 MHz with the clock pulse matching the stress voltage applied on
the chips. A green LED carefully designed and tuned on each testing
board served as the light source within the chamber for Linearity and
Photon Response Non-Uniformity measurements. A typical clock
frequency during the mission operating condition is 4MHz.
The imagers were first characterized under each stress
temperature condition to determine an appropriate integration time.
The integration time was chosen to be 30ms during FPN and PRNU
measurements to represent the mission operating condition. The
integration time during dark rate and Linearity measurements was
chosen long enough for the imagers to reach saturation region for a
full characterization of the imaging response.
CHIP RELIABILITY PROJECTION
For overall VIDI APS chip reliability, Linearity and Dark
Rate are the two parameters to be considered since they reflect the
overall parametric shift or change on the imaging chips.
Figure 4 shows the linearity characteristics for the worst
case chip as a function of stress time. The black symbol indicates the
response at time zero while the white symbol indicates response at
the end of stress testing. The characteristics trend is representative
for all imaging chips under all stress conditions.
time (ms)
0 20 40 60 80 100 120 140 160 180
linearity (mV/s)
0
200
400
600
800
1000
1200
1400
Figure 4. Linearity changes with stress time, black symbols indicate
time zero, white symbols indicate at the end of stress.
Agilent 33120A
Function Generator
Agilent 3631A
DC Power Supply
PC
Interface
Board
APS chips
Stressed
In Parallel

Figure 4 indicates that it took a longer integration time to
achieve saturation when the device was degraded. This information
can be also presented by the slope of the linearity curves before the
saturation points. The percentage of the slope change of the linearity
curves in Figure 4 is plotted in Figure 5, showing almost linear
increasing Linearity slope versus stress time in a log-log scale.
stress time (s)
1e+5 1e+6 1e+7
Linearity slope change (%)
1
10
100
Figure 5. Linearity slope change with stress time.
The behavior of the dark rate is similar to that of Linearity
but with smaller degradation rate. Figure 6 shows a representative
change of the dark rate slope as a function of stress time in a log-log
scale.
stress time (s)
1e+5 1e+6 1e+7
Dark Rate slope change (%)
0.1
1
10
Figure 6. Dark rate slope change with stress time.
Since the Dark Rate and Linearity can indicate the overall
sensor performance, the sensor’s overall chip reliability can be
projected based on the Dark Rate and Linearity degradation.
Assuming the Arrhenius model [12]
o
a
o
kT
E
V
eet
β
~
%
where t
%
is the chip life time at certain failure fraction and is
determined to be 0.1% in our case; β, V
o
, E
a
, k and T
o
are the
voltage acceleration factor, operating voltage, activation energy,
Boltzmann’s constant and operating temperature in Kelvin,
respectively.
The voltage acceleration factor and activation energy were
estimated as 0.73 dec/volt and 0.7eV, respectively, for worst case
imaging chips. Using 10% degradation for Linearity as the chip
failure criterion, the chip life time at 3.3V, 27°C is over 112 years at
0.1% failure fraction with average failure rate of 1 FIT. Life and
failure rate can be also generated by using a percentage degradation
of Dark Rate as well.
It should be noted that the “failure” criteria used in this
reliability projection is defined as a certain level of parametric
shifting. Even though this parametric shifting does indicate some
performance degradation of the imagers, it is worthwhile to note that
the imagers still frame and function very well when the Dark Rate
and/or Linearity reaches 10% parametric degradation. In order to
estimate life and failure rate associated with the “imaging failures”,
pixel reliability needs to be projected.
PIXEL RELIABILITY PROJECTION
In the previous section, chip reliability projection indicates
reliability for a sensor’s overall performance as a function of
operation time, but it is difficult to relate it to image quality.
Therefore, pixel reliability needs to be considered and projected as
well.
The Dark Current Non-Uniformity, Fixed Pattern Noise
and Photon Response Non-Uniformity measurements during the
accelerated testing recorded the distributions of the photodiode
reference voltage for each pixel as a function of stress time, in order
to calculate the time-dependent DCNU, FPN and PRNU values.
Figure 7 shows an example of the distributions of pixel
responses during FPN measurements with FPN suppression function
enable at 27°C.
0
1000
2000
3000
4000
5000
6000
7000
-3 -2 -1 0 1 2 3
Reference Voltage
Frequency
Figure 7. Pixel response during FPN measurement at 27°C.
During the accelerated testing, some of the pixels get
“hotter”, i.e. leak more than nominal pixels. In addition, the standard
deviation of the pixel distribution increases slightly with worst case
of 2% change, and the median of the distribution eventually shifts.
Based on our sample size of 20 CMOS active pixel
sensors (18 for accelerated testing and 2 for characterization testing)
with 512 by 512 pixels on each imager, we found that the “hot”
pixels tend to be randomly distributed across the pixel array and no

signature of the pattern can be found. This may indicate that the
imaging chips do not have evident process-related defects or stress-
induced weak-link pixels. The hot pixel generation rate is slow at
the accelerated stress levels. Based on the limited data, the estimated
hot pixel generation rate is approximately one and one-half pixel per
decade at 6V 85°C, which gives a rather long projected imager life,
assuming a few hot pixels do not have a severe impact on imaging
quality. Hot pixels do not seem to induce neighboring pixel to
degrade faster. Hot pixels can cause image problems but with a
proper refreshing scheme, the impact of hot pixel on imaging quality
can be significantly reduced.
The change in standard deviation of the pixel distribution
seems to increase faster at the beginning of the accelerated stress
conditions and then saturates at about 2% to 3% change. However,
due to the limited data sets and small sample size in our study, no
further conclusion can be made on the behavior of the standard
deviation change.
When the pixel distributions under DCNU, FPN and
PRNU measurements have shifted and/or the standard deviations
have changed, it indicates a change in black-white scale for imaging.
Therefore, by scaling the time-dependent pixel distribution against
the initial pixel distribution, images can be generated either by real
pixel distribution data or by projected pixel distributions.
The pixel distributions for DCNU, FPN and PRNU did not
have significant shift during our accelerated testing. This can be
expected since the minimum channel length of the active transistor
inside the pixel cell is rather long, i.e. 0.5 um. Therefore, based
on the trend of pixel degradation, the projected pixel distributions
can be and needed to be generated to simulate the image quality.
Figure 8 shows an original image of Saturn. Figure 9, 10
and 11 are the simulated images with 10%, 15% and 20% median
pixel degradation, respectively. The degradation on the imaging
quality can be seen very clearly from these Figures, thus a so-called
“imaging failure” can be determined based on the series of images.
For example, if Figure 8 is regarded as an imaging fail, a 10%
median pixel degradation is then chosen as the failure criterion. In
this case, the imager life is at least an order of magnitude longer than
the projected imager life using 10% Linearity degradation.
Figure 8. Original image of Saturn
Figure 9. Image with pixel degradation
(Median percentage change is 10%).
Figure 10. Image with pixel degradation
(Median percentage change is 15%).
Figure 11. Image with pixel degradation
(Median percentage change is 20%).
Figure 8-11. Imaging quality simulation with different level of pixel
degradation.

Another failure mechanism results from the read-out or
I/O circuitry. It happens rather suddenly when the imager stops
functional totally. Competing with the pixel degradation, which is a
relatively slower process, periphery circuitry failure may be much
more severe since it will cause a hard failure of the imager. This
happened during radiation testing when the imager failed in a
sudden owing to the periphery circuit failure.
The pixel reliability is a function of acceptable image
quality level and depends on the pixel responses to darkness and
light. Acceptable image quality can be chosen based on the same
experimental data or simulation results using small degradation
percentage increases. It should be noted that the reliability projection
based on the worst case parameter degradation, i.e. linearity
degradation, gives a much shorter lifetime prediction compared to
the pixel projection. Therefore, pixel reliability cannot be
overlooked during imaging sensor qualification.
SUMMARY
A reliability study on a CMOS active pixel sensor imaging
system is presented. While a reliability projection based on the
imaging sensor’s overall parametric performance may provide some
insight on the imager performance degradation, pixel reliability
projection, either by experimental or by predicted pixel distributions,
has to be performed. The projected pixel reliability can be directly
related to imaging quality and provide additional sensor
performance information.
REFERENCES
1. E. R. Fossum, “CMOS Image Sensors: Electronic Camera-
on-a-Chip”, IEEE Transactions on Electron Devices, Vol.
44, No. 10, pp. 1689-1697, October, 1997.
2. J. Janesick, “Lux transfer: Complementary metal oxide
semiconductors versus charge-coupled devices”, Opt. Eng.
41(6), 1203-1215, June, 2002.
3. F. Pardo, et al, “CMOS Foveated Image Sensor: Signal
Scaling and Small Geometry Effects”, IEEE Transactions
on Electron Devices, Vol. 44, No. 10, pp. 1731-1737,
October, 1997.
4. D. Scheffer, et al, “Random Addressable 2048 X 2048
Active Pixel Image Sensor”, IEEE Transactions on
Electron Devices, Vol. 44, No. 10, pp. 1716-1720,
October, 1997.
5. S. Mendis, et al, “CMOS Active Pixel Image Sensor”,
IEEE Transactions on Electron Devices, Vol. 41, No. 3,
pp. 452-453, March, 1997.
6. G. Deptuch, et al, “Design and Testing of Monolithic
Active Pixel Sensor for Charged Particle Tracking”, IEEE
Transactions on Nuclear Science, Vol 49, No. 2, p601-
610, 2002.
7. J. Nakamura, et al, “On-focal-plane signal processing for
current-mode active pixel sensors”, IEEE Transactions on
Electron Devices, Vol 44, pp. 1747-1758, 1997.
8. R.H. Nixon, et al, “128 X 128 CMOS photodiode-type
active Pixel Sensor with on-chip Timing Control and
Signal Chain Electronics”, Charge-Coupled Devices and
Solid-State Optical Sensors V, Proceedings of SPIE, Vol.
2415, pp. 117-123, 1995.
9. O. Yadid-Petch and E.R. Fossum, “Wide Intrascene
Dynamic Range CMOS APS Using Dual Sampling”,
IEEE Transactions on Electron Devices, Vol 44, pp. 1721-
1723, 1997.
10. L. Scheick, F. Novak, “Hot Pixel Generation in Active
Pixel Sensors: Domeimetric and Microdosimetric
Response”, Radiation and its Effects on Component and
Systems, Noorwikj, Netherlands, September, 2003.
11. N. Ricquier and B. Dierickx, “Pixel Structure with
Logarithmic Response for Intelligent and Flexible Imager
Architectures”, Microelectron. Eng., Vol. 19, pp. 631-
634, 1992.
12. W. Nelson, “Accelerated Testing”, John Wiley & Sons,
New York, 1990.
ACKNOWLEDGEMENTS
This work was carried out at Jet Propulsion Laboratory,
California Institute of Technology, under a contract with the
National Aeronautics and Space Administration. The authors also
would like to thank Dr. Bedabrata Pain and Chris Wrigley for
helpful technical discussions.
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121 citations


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Q1. What contributions have the authors mentioned in the paper "A chip and pixel qualification methodology on imaging sensors" ?

This paper presents a qualification methodology on imaging sensors. The projected pixel reliability is directly related to imaging quality and provides additional sensor reliability information and performance control. [