# A clustering technique for fast electrothermal analysis of on-chip power distribution networks

Abstract: This paper presents an equivalent self-consistent electrothermal circuit model for power integrity analysis of large on-chip power distribution networks. Two coupled circuits are used to co-simulate the electrical and thermal behavior of the power grid. After a steady-state analysis, the order of the circuit is strongly reduced by means of a node clustering technique. The obtained low-order circuit allows a cost-effective complete power integrity analysis, including dynamic analysis and evaluation of time-domain features like voltage droop. As a case-study, a 45-nm chip power grid is analyzed: the full circuit for the electrothermal model with 4 million nodes is reduced by a factor of about 3500×, with a relative error on the solution below few percent.

## Summary (2 min read)

### I. INTRODUCTION

- The temperature increase related to power dissipation in onchip Power Distribution Networks (PDNs) may strongly affect the electrical performance of such networks in conventional VLSI architectures (e.g. [1] ) or innovative 3D ICs (e.g. [2] ).
- Reaching the convergence to a fixed accuracy stops the cycle.
- In principle, the solution of the thermal model may require a full-3D numerical simulation of the problem (via FD, FEM or BEM methods, for instance).
- In such a case, a simple equivalent electrical network is used (see Fig. 1 ), where an equivalence is established between temperature and voltage, heat flow and electrical current, thermal and electrical resistance and capacitance, heat production and current source, initial temperature and voltage source.
- Therefore, modest results can be achieved for PDNs when using popular model-order reduction techniques suitable for signal interconnects, such as those based on subspace projections [5] - [7] .

### II. ELECTRO-THERMAL MODEL

- The authors consider a standard PDN structure as the one depicted in Fig. 2 , where two conductor grids are connected to VDD and GND supply pins, respectively.
- The VDD grid is connected to package by a series impedance Zsupply (not shown here), whereas the GND grid nodes are connected to a heatsink, for heat dissipation purposes.
- The solution of the electrical problem provides the so-called voltage drop at any generic node i, namely: EQUATION being Vn(i) and Vg(i) the node potentials with respect to the power and ground plane references, respectively.
- As pointed out in the introduction, the thermal circuit solution depends on the electrical solution via the equivalent controlled current source in Fig. 3b , which models the heat generation produced by: (i) the switching activity, PS(i)=I0Vd(i); (ii) the Joule effect into the conductors connected to such a node, PJ(i).
- If necessary, different quantization steps NV and NT can be chosen for the electrical and thermal problem, respectively, due the different nature of the two physical problems.

### STEP 5. Synthesize (4) into a SPICE netlist. ♦

- The final electrical circuit contains 2NV nodes; such a number depends, of course, on the chosen quantization, i.e., on the desired accuracy.
- The great advantage of the proposed procedure resides in the fact that the analysis of the complete networks is performed only in steady state condition, whereas the power integrity analysis is performed with the SPICE reduced circuit.
- In principle, the steady state analysis can be also carried out at a frequency different from zero.
- Nevertheless, since the power in PDNs is mainly associated to the DC component, and assuming that the physical dimensions are such that no resonance falls into the frequency band of interest, the authors verified that the clustering obtained by using the DC solution did not change if an AC signal was superimposed.

### IV. RESULTS

- A 1020×1020 grid was assumed for each PDN plane (VDD and GND planes), which means that each electrical grid contains about 1 million nodes.
- The authors investigated the 45nm technology, whose typical parameters are reported in Table I [11] .
- Assuming the same quantization as for the basic stamp, the clustering procedure provides a reduced electrical circuit of 300 nodes for each plane, with a reduction factor of 3468x.
- The reduced SPICE circuit was synthesized and used to perform noise analysis on PDN to retrieve the voltage droop, which was estimated to be 75.53 mV for the same feeding conditions as in Table III .
- Finally, to have a quantitative measure of the computational cost, the authors used a PC with 32GB RAM and a quad-core processor, equipped with HSPICE version G-2012.06 [13] .

### V. CONCLUSIONS

- The paper presented a clustering technique able to strongly reduce the computational cost of the electrothermal analysis of large chip power distribution networks, both for the DC and dynamical cases.
- The full network analysis is limited to a steady-state simulation, much less costly than the full dynamic solution of the electrothermal problem.
- The dynamic analysis of the PDN is then carried out with the obtained SPICE reduced order circuit.

Did you find this useful? Give us your feedback

...read more

##### Citations

##### References

378 citations

128 citations

121 citations

### "A clustering technique for fast ele..." refers background in this paper

...In addition, it is well-known that the PDN thermal behavior is strictly related to reliability issues like electromigration [3]....

[...]

102 citations

### "A clustering technique for fast ele..." refers background in this paper

...Recently, new reduction approaches have been proposed for electrical networks, based on the concept of node reduction [8]-[9]....

[...]

...In the following we assume that the grid discretization is fine enough that the branch lengths are smaller than or equal to the characteristic thermal length: in this case, we can adopt the same grid for the electrical and thermal problems [9]....

[...]

17 citations