# A clustering technique for fast electrothermal analysis of on-chip power distribution networks

08 May 2016-pp 1-4

TL;DR: In this article, a self-consistent electrothermal circuit model for power integrity analysis of large on-chip power distribution networks is presented, where two coupled circuits are used to co-simulate the electrical and thermal behavior of the power grid.

Abstract: This paper presents an equivalent self-consistent electrothermal circuit model for power integrity analysis of large on-chip power distribution networks. Two coupled circuits are used to co-simulate the electrical and thermal behavior of the power grid. After a steady-state analysis, the order of the circuit is strongly reduced by means of a node clustering technique. The obtained low-order circuit allows a cost-effective complete power integrity analysis, including dynamic analysis and evaluation of time-domain features like voltage droop. As a case-study, a 45-nm chip power grid is analyzed: the full circuit for the electrothermal model with 4 million nodes is reduced by a factor of about 3500×, with a relative error on the solution below few percent.

## Summary (2 min read)

Jump to: [I. INTRODUCTION] – [II. ELECTRO-THERMAL MODEL] – [STEP 5. Synthesize (4) into a SPICE netlist. ♦] – [IV. RESULTS] and [V. CONCLUSIONS]

### I. INTRODUCTION

- The temperature increase related to power dissipation in onchip Power Distribution Networks (PDNs) may strongly affect the electrical performance of such networks in conventional VLSI architectures (e.g. [1] ) or innovative 3D ICs (e.g. [2] ).
- Reaching the convergence to a fixed accuracy stops the cycle.
- In principle, the solution of the thermal model may require a full-3D numerical simulation of the problem (via FD, FEM or BEM methods, for instance).
- In such a case, a simple equivalent electrical network is used (see Fig. 1 ), where an equivalence is established between temperature and voltage, heat flow and electrical current, thermal and electrical resistance and capacitance, heat production and current source, initial temperature and voltage source.
- Therefore, modest results can be achieved for PDNs when using popular model-order reduction techniques suitable for signal interconnects, such as those based on subspace projections [5] - [7] .

### II. ELECTRO-THERMAL MODEL

- The authors consider a standard PDN structure as the one depicted in Fig. 2 , where two conductor grids are connected to VDD and GND supply pins, respectively.
- The VDD grid is connected to package by a series impedance Zsupply (not shown here), whereas the GND grid nodes are connected to a heatsink, for heat dissipation purposes.
- The solution of the electrical problem provides the so-called voltage drop at any generic node i, namely: EQUATION being Vn(i) and Vg(i) the node potentials with respect to the power and ground plane references, respectively.
- As pointed out in the introduction, the thermal circuit solution depends on the electrical solution via the equivalent controlled current source in Fig. 3b , which models the heat generation produced by: (i) the switching activity, PS(i)=I0Vd(i); (ii) the Joule effect into the conductors connected to such a node, PJ(i).
- If necessary, different quantization steps NV and NT can be chosen for the electrical and thermal problem, respectively, due the different nature of the two physical problems.

### STEP 5. Synthesize (4) into a SPICE netlist. ♦

- The final electrical circuit contains 2NV nodes; such a number depends, of course, on the chosen quantization, i.e., on the desired accuracy.
- The great advantage of the proposed procedure resides in the fact that the analysis of the complete networks is performed only in steady state condition, whereas the power integrity analysis is performed with the SPICE reduced circuit.
- In principle, the steady state analysis can be also carried out at a frequency different from zero.
- Nevertheless, since the power in PDNs is mainly associated to the DC component, and assuming that the physical dimensions are such that no resonance falls into the frequency band of interest, the authors verified that the clustering obtained by using the DC solution did not change if an AC signal was superimposed.

### IV. RESULTS

- A 1020×1020 grid was assumed for each PDN plane (VDD and GND planes), which means that each electrical grid contains about 1 million nodes.
- The authors investigated the 45nm technology, whose typical parameters are reported in Table I [11] .
- Assuming the same quantization as for the basic stamp, the clustering procedure provides a reduced electrical circuit of 300 nodes for each plane, with a reduction factor of 3468x.
- The reduced SPICE circuit was synthesized and used to perform noise analysis on PDN to retrieve the voltage droop, which was estimated to be 75.53 mV for the same feeding conditions as in Table III .
- Finally, to have a quantitative measure of the computational cost, the authors used a PC with 32GB RAM and a quad-core processor, equipped with HSPICE version G-2012.06 [13] .

### V. CONCLUSIONS

- The paper presented a clustering technique able to strongly reduce the computational cost of the electrothermal analysis of large chip power distribution networks, both for the DC and dynamical cases.
- The full network analysis is limited to a steady-state simulation, much less costly than the full dynamic solution of the electrothermal problem.
- The dynamic analysis of the PDN is then carried out with the obtained SPICE reduced order circuit.

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A clustering technique for fast electrothermal analysis of

on-chip power distribution networks

Alessandro Magnani, Massimiliano De Magistris, Antonio Maucci, Aida

Todri-Sanial

To cite this version:

Alessandro Magnani, Massimiliano De Magistris, Antonio Maucci, Aida Todri-Sanial. A clustering

technique for fast electrothermal analysis of on-chip power distribution networks. SPI: Signal and

Power Integrity, May 2016, Turin, Italy. �10.1109/SaPIW.2016.7496292�. �lirmm-01446283�

A Clustering Technique for Fast Electrothermal

Analysis of On-Chip Power Distribution Networks

A. Magnani, M. de Magistris

Dep. of Electrical Engineering and

Information Technology

University Federico II, Naples, Italy

alessandro.magnani@unina.it

m.demagistris@unina.it

A. Maffucci

Dep. of Electrical and

Information Engineering

University of Cassino and S.L.

Cassino, Italy

maffucci@unicas.it

A. Todri-Sanial

CNRS- LIRMM

University of Montpellier

Montpellier, France

todri@lirmm.fr

Abstract—This paper presents an equivalent self-consistent

electrothermal circuit model for power integrity analysis of large

on-chip power distribution networks. Two coupled circuits are

used to co-simulate the electrical and thermal behavior of the

power grid. After a steady-state analysis, the order of the circuit is

strongly reduced by means of a node clustering technique. The

obtained low-order circuit allows a cost-effective complete power

integrity analysis, including dynamic analysis and evaluation of

time-domain features like voltage droop. As a case-study, a 45-nm

chip power grid is analyzed: the full circuit for the electrothermal

model with 4 million nodes is reduced by a factor of about 3500x,

with a relative error on the solution below few percent.

Keywords— On-chip power distribution networks; IR-drop;

model order reduction; electrothermal analysis, power integrity.

I. INTRODUCTION

The temperature increase related to power dissipation in on-

chip Power Distribution Networks (PDNs) may strongly affect

the electrical performance of such networks in conventional

VLSI architectures (e.g. [1]) or innovative 3D ICs (e.g. [2]). In

addition, it is well-known that the PDN thermal behavior is

strictly related to reliability issues like electromigration [3]. As

a consequence, a self-consistent electrothermal modeling is

needed to get accurate power integrity analysis and a reliable

design of PDNs.

The thermal problem is coupled to the electric one via the

heat production term, which depends on electrical power

dissipated for device activity and for joule effects in the grid

conductors. On the other side, the electrical problem is related

to the solution of the thermal one since the electrical

parameters, such as the resistance, depend on temperature.

Usually the electrothermal co-simulation system consists in

solving these coupled problems with a relaxation approach:

(i) the heat production term is evaluated at initial temperature;

(ii) solving heat equation provides the temperature distribution;

(iii) the temperature-dependent electrical parameters are

updated and the electrical problem is solved;

(iv) the heat production term is updated.

Reaching the convergence to a fixed accuracy stops the cycle.

In principle, the solution of the thermal model may require

a full-3D numerical simulation of the problem (via FD, FEM or

BEM methods, for instance). This approach accurately

describes 3D geometries and accounts for air convection or

cooling effects, but at extremely high computational cost [4].

However, in many cases of practical interest, in PDN structures,

materials are homogeneous and the heat mainly flows along the

grid conductors (grids and vias), being negligible the heat

exchange between copper and dielectric. In such a case, a

simple equivalent electrical network is used (see Fig.1), where

an equivalence is established between temperature and voltage,

heat flow and electrical current, thermal and electrical

resistance and capacitance, heat production and current source,

initial temperature and voltage source. The main advantage of

this approach resides, of course, in the possibility of handling

the electro-thermal modeling in the common frame of SPICE-

like simulators. However, PDNs are very complicated

structures including power planes, metal traces, chips,

packages, decaps, vias and controlled collapse chip connection

(C4) bumps [2], and thus even describing each subpart with a

simple electrical RLC model and with the equivalent thermal

model in Fig.1, the size of an equivalent network describing

PDNs easily reaches the order of several millions of nodes.

Dynamic analysis (for instance noise analysis) of such large

networks is likely to be unaffordable, hence reducing the

computational cost of simulations has become a major issue.

Unlike the signal interconnects, where the propagation

plays a fundamental role, hence any accurate circuit model must

handle a huge number of poles, a PDN is usually characterized

by a huge number of nodes, but at a low number of poles.

Therefore, modest results can be achieved for PDNs when using

popular model-order reduction techniques suitable for signal

interconnects, such as those based on subspace projections [5]-

[7]. Recently, new reduction approaches have been proposed

for electrical networks, based on the concept of node reduction

[8]-[9].

In [10] the Authors have proposed a novel model-order

reduction technique based on the concept of node clustering. A

preliminary steady state solution of the Electrothermal (ET)

problem provides the distributions of temperature and voltage

drop values at each node of the PDN. Choosing a quantization

for temperature and voltage drop the nodes are then clustered

Fig.1 Simple equivalent electrical model for the thermal problem.

978-1-5090-0349-5/16/$31.00 ©2016 IEEE

into supernodes and a reduced order circuit is obtained where

the thermal and electrical interactions take place between

supernodes. In [10] the model was limited to steady state

analysis, and thus only the resistive elements were taken into

account. In the present paper the work has been completed by

including the dynamic parts and by extending the study to AC

and to time domain noise analysis, thus providing a complete

tool for PDN power integrity.

In Section II the electro-thermal model is briefly revised,

whereas Section III introduces the clustering technique. A case

study is provided in Section IV, referring to a 45nm chip PDN.

II. E

LECTRO

-T

HERMAL

M

ODEL

We consider a standard PDN structure as the one depicted

in Fig.2, where two conductor grids are connected to VDD and

GND supply pins, respectively. The VDD grid is connected to

package by a series impedance Z

supply

(not shown here), whereas

the GND grid nodes are connected to a heatsink, for heat

dissipation purposes. The electrical model describing the

interaction of each single node with neighborhood is depicted

in Fig.3a: each interconnect between the node and any adjacent

node in the same grid is modeled as an R-L series, whereas the

connection between corresponding nodes of different grids is

modeled by a capacitor in parallel with a current source I

0

. The

latter represents the circuit switching activity, i.e. the current

demand of a circuit connected between VDD and GND pins.

The solution of the electrical problem provides the so-called

voltage drop at any generic node i, namely:

))()(()( iViVViV

gnDDd

−−=

, (1)

being V

n

(i) and V

g

(i) the node potentials with respect to the

power and ground plane references, respectively.

The temperature distribution over the grid nodes is obtained

by solving the thermal problem, modeled by the equivalent

circuit in Fig.3b. In the following we assume that the grid

discretization is fine enough that the branch lengths are smaller

than or equal to the characteristic thermal length: in this case,

we can adopt the same grid for the electrical and thermal

problems [9]. The thermal resistances R

TH

and R

HS

correspond

to the PDN segments in the same grid, and to the connections

to heatsink, respectively. Note that the thermal capacitor in

Fig.1 is omitted, which means that the dynamic behavior of

thermal solution is neglected, which is a realistic assumption in

the considered problem, being the time scales of the thermal

problem much greater than those of the electrical one.

As pointed out in the introduction, the thermal circuit

solution depends on the electrical solution via the equivalent

controlled current source in Fig.3b, which models the heat

generation produced by: (i) the switching activity,

P

S

(i)=I

0

V

d

(i); (ii) the Joule effect into the conductors connected

to such a node, P

J

(i). The electrical circuit solution depends on

the thermal solution by means of the classical relation between

conductor resistivity and temperature:

0 0

( ) (1 ),

ρ ρ α

= +

r

T T

(2)

where T

r

=T-T

0

is the temperature rise with respect to a

reference value T

0

. For copper conductors and T

0

= 300 K, it is

ρ

0

=1.72×10

-8

Ωm and α

0

=0.0039 K

-1

. The two problems are

coupled in a classical relaxation approach.

Fig.2 The considered power delivery network structure.

Fig.3 Electrical (a) and thermal (b) circuit model at each grid node.

III. O

RDER

R

EDUCTION BY

N

ODE

C

LUSTERING

The ET model consists in an electrical and a thermal

network, each of them containing two grids (VDD and GND)

of N nodes. The clustering technique proceeds as follows:

STEP 1. Solve ET problem for the full model in steady-state

condition. This provides the distributions of voltage drop on

electrical nodes and of temperature on thermal ones.

STEP 2. Define a quantization V

dk

, with k=1,..N

V

(T

rh

, with

h=1,..N

T

) for the voltage drop V

d

(the temperature rise T

r

). For

uniform quantization, the levels are separated by:

(

)

( )

).1/(

),1/(

min,max,

min,max,

−−=∆

−−=∆

Trrr

Vddd

NTTT

NVVV

(3)

If necessary, different quantization steps N

V

and N

T

can be

chosen for the electrical and thermal problem, respectively, due

the different nature of the two physical problems.

STEP 3. Cluster in the k-th electrical supernode each electrical

node i such that:

ddkd

VViV ∆≤−)(

. Cluster in the h-th thermal

supernode each thermal node j such that:

rrhr

TTjT ∆≤−)( .

STEP 4. Build the incidence matrices

A

e

and

A

t

and the

admittance matrices

Y

e

and

Y

t

of the reduced electrical and

thermal networks, respectively. Matrix

A

e

is easily obtained by

checking the correspondence between original nodes and final

supernodes. The generic element (k,m) of

Y

e

(corresponding to

supernodes “k” and “m”) is obtained by summing up all the

admittances

ij

Y of the original electrical network, such that

. , mjki

∈

∈

Finally, the equivalent current sources to be

inserted between supernodes k and m are obtained by summing

all the sources terms

0

I

, inserted between a pair of nodes (i,j),

being

., mjki ∈∈

After this step, we obtain the circuit model:

,

0

IV

d

er

=Y

,

ee

T

eer

AYAY =

(4)

The same approach is applied for the thermal network.

STEP 5. Synthesize (4) into a SPICE netlist.

♦

The final electrical circuit contains 2N

V

nodes; such a

number depends, of course, on the chosen quantization, i.e., on

the desired accuracy. The great advantage of the proposed

procedure resides in the fact that the analysis of the complete

networks is performed only in steady state condition, whereas

the power integrity analysis is performed with the SPICE

reduced circuit. In principle, the steady state analysis can be

also carried out at a frequency different from zero.

Nevertheless, since the power in PDNs is mainly associated to

the DC component, and assuming that the physical dimensions

are such that no resonance falls into the frequency band of

interest, we verified that the clustering obtained by using the

DC solution did not change if an AC signal was superimposed.

IV.

R

ESULTS

The analyzed case-study was a standard PDN with the

structure as in Fig.2, referred to a core of dimensions 20 mm x

20 mm. A 1020×1020 grid was assumed for each PDN plane

(VDD and GND planes), which means that each electrical grid

contains about 1 million nodes. As pointed out in Section 3, the

same grid was used for the equivalent thermal circuit, thus the

total number of nodes is about 4 millions. The structure was

obtained by a 20×20 replica of a basic stamp made of 2601

(51×51) nodes. The basic stamp was fed at its four corners,

where it was connected through C4 bumps to the package

through a package impedance Z

supply

. Each grid branch was

made by a copper conductor with section WxH and length l. We

investigated the 45nm technology, whose typical parameters

are reported in Table I [11]. Note that the range of values for I

0

corresponds to chip power density 1.5 µW/µm

2

, which is a

typical value for such a technology [11]. The electrical and

thermal circuit parameters reported in Table II were estimated

through the Predictive Technology Model [12].

The temperature and voltage drop distributions on the basic

stamp (51×51 nodes), provided by the preliminary full DC

analysis, are reported in Fig.4. Assuming uniform quantization

with N

V

=55 and N

T

=77, (which correspond to

K 32.0=∆

r

T

and

mV 74.0=∆

d

V

), the clustering procedure provides a

reduced electrical circuit of 55 nodes (instead of 2601) for each

VDD and GND plane, with a reduction factor of 47x. As a proof

of consistency for the DC solution, the synthesized low-order

SPICE circuit was used to reproduce the

TABLE I

T

YPICAL

P

ARAMETERS FOR A

45-

NM

PDN

[11]

W [µm] H [µm] l [µm] V

DD

[V]

I

0

[mA]

10 1 1000 1 0.577

TABLE II

C

IRCUIT

P

ARAMETERS FOR

E

LECTRICAL AND THERMAL

M

ODELS

R

[mΩ]

C

[pF]

L

[nH]

R

supp

[Ω]

L

supp

[nH]

R

TH

[kK/W]

R

HS

[MK/W]

21.56

3.845 0 0.01 60 2545 0.25

TABLE III

V

OLTAGE

D

ROOP

E

STIMATED WITH

F

ULL AND

R

EDUCED

C

IRCUITS

Stimulus

(waveform)

Full

circuit

Reduced

circuit

Relative

error [%]

Triangular 95.938 mV 90.502 mV 5.67%

map in Fig.4b: the relative error distribution provided in Fig.5

clearly proofs the consistency.

To check also consistency for transient solutions, we

compared the maximum voltage droop provided by the full and

reduced circuits, see Table III. The voltage droop at each node

was evaluated by stimulating the PDN with a periodic triangle-

wave current, integrating each voltage over a period, and

dividing for the period itself. The stimulus triangular waveform

was characterized by base level of 0.577 mA, peak I

peak

=0.769

mA, t

rise

=50 ps, t

peak

=10 ps, and t

fall

=100 ps [2].

Fig.4 Steady-state maps: (a) temperature rise (in K); (b) and voltage drop (in V)

for the 51x51 PDN.

Fig.5 Percent relative error in the voltage drop distribution estimated by the

SPICE reduced order circuit, for the basic stamp 51x51 PDN.

(a)

(b)

(V)

(K)

After the consistency check on the basic stamp, the

clustering procedure was applied to the full ET model of the

chip with 4 million nodes. The preliminary steady state analysis

provided the temperature and voltage drop distributions, as

shown in Fig.6. Assuming the same quantization as for the basic

stamp, the clustering procedure provides a reduced electrical

circuit of 300 nodes for each plane, with a reduction factor of

3468x. A consistency proof showed that the reduced circuit is

Fig.6 Steady-state maps: (a) temperature rise (in K) and (b) voltage drop (in V)

for the 1020x1020 PDN.

Fig.7 Percent relative error for temperature rise (right axis) and voltage drop

(let axis) for the full chip analysis, as a function of the reduction factor.

able to reproduce the maps in Fig.6 with a maximum error of

about 0.4% in voltage and 2.5% in temperature (see Fig.7). The

reduction factor may be lowered when a better accuracy is

required, as shown in Fig.7.

The reduced SPICE circuit was synthesized and used to

perform noise analysis on PDN to retrieve the voltage droop,

which was estimated to be 75.53 mV for the same feeding

conditions as in Table III.

Finally, to have a quantitative measure of the computational

cost, we used a PC with 32GB RAM and a quad-core processor,

equipped with HSPICE version G-2012.06 [13]. With such a

configuration, the full chip cannot be simulated by HSPICE

because of the too large number of dynamic elements. The

preliminary steady-state solution (including several iteration of

the relaxation cycle) took 60 s, while additional 10s are needed

for the reduction process. The HSPICE simulation on the

reduced circuit took 6.2s.

V.

C

ONCLUSIONS

The paper presented a clustering technique able to strongly

reduce the computational cost of the electrothermal analysis of

large chip power distribution networks, both for the DC and

dynamical cases. The full network analysis is limited to a

steady-state simulation, much less costly than the full dynamic

solution of the electrothermal problem. The dynamic analysis

of the PDN is then carried out with the obtained SPICE reduced

order circuit. The analyzed case-studies demonstrated the

consistency of the technique and its capability of reducing the

complexity of a grid of 4 million node by a factor of about 3500.

R

EFERENCES

[1] Y.-K. Cheng, C.-H. Tsai, C.-C. Teng, S.-M. Kang, Electrothermal

Analysis of VLSI Systems,Springer, 2002.

[2] A. Todri-Sanial and C. Seng Tan, Physical Design for 3D Integrated

Circuits, CRC Press, ISBN: 9781498710367, 2015.

[3] A. Christou and M. Peckerar, Electromigration and Electronic Device

Degradation, Wiley and Sons, 1994.

[4] M. Pedram, and S. Nazarian, “Thermal modeling, analysis, and

management in VLSI circuits: principles and methods,” Proceedings of

the IEEE, vol. 94, pp.1487–1501, 2006.

[5] M. de Magistris, M. Nicolazzo “On the Concretely Passive Realization of

Reduced Circuit Models Based on Convex Constrained Positive Real

Fractions Identification,” proc. of IEEE Workshop on Signal Propagation

on Interconnects, SPI 2011, pp.29-32, Napoli (Italy) 8-11 May 2011.

[6] S. Grivet-Talocia, “Package macromodeling via time-domain vector

fitting,” IEEE Microwave and Wireless Components Letters, Vol.13, pp.

472 – 474, 2003.

[7] M. De Magistris, L. De Tommasi, A. Maffucci, G. Miano “Low-Order

Identification of Interconnects with the Generalized Method of

Characteristics”, IEEE Trans. on Electromagnetic Compatibility, Vol.49,

pp.670-676, 2007.

[8] Z. Zhang, X. Hu, C. K. Cheng, and N. Wong, “A block-diagonal

structured model reduction scheme for power grid networks,” in Proc.

IEEE Design Automation & Test in Europe (DATE), 2011.

[9] Yu Zhong, “Fast algorithms for IR drop analysis in large power grid,” in

Proc. of the IEEE/ACM ICCAD, pp. 351-357, 2005.

[10] A.Magnani, M. de Magistris, A. Maffucci, A. Todri-Sanial, “A node

clustering reduction scheme for power grids electrothermal analysis” in

Proc. IEEE Work. on Signal and Power Integrity (SPI), 2015, pp.74-77.

[11] International Technology Roadmap for Semiconductors, 2013,

http://public.itrs.net

[12] Predictive Technology Model, http://ptm.asu.edu/

[13] HSPICE G.2012.06, Reference Manual: Commands and Control Options,

Synopsys Inc., 2012.

(V)

(K)

(a)

(b)

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25 Sep 2006TL;DR: A brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power V LSI circuits is presented.

Abstract: The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

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TL;DR: In this article, a technique named Time Domain Vector Fitting (TD-VF) is introduced for the identification of the dominant poles of the structure, which uses as raw data transient excitations and responses at the ports of the package structure.

Abstract: This paper addresses the construction of lumped macromodels for package structures. A technique named Time-Domain Vector Fitting (TD-VF) is introduced for the identification of the dominant poles of the structure. This method uses as raw data transient excitations and responses at the ports of the structure. These responses are easily obtained from transient full-wave electromagnetic solvers based, e.g., on Finite Differences. The rational approximation can be easily synthesized into a SPICE-compatible subcircuit providing a broadband approximation to the input-output behavior of the package.

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### "A clustering technique for fast ele..." refers background in this paper

...In addition, it is well-known that the PDN thermal behavior is strictly related to reliability issues like electromigration [3]....

[...]

••

31 May 2005TL;DR: Two iterative algorithms based on node-by-node traversals and row- by-row traversals of the power grid, respectively are presented and can be considered as efficient implementations of the classical successive over relaxation iterative method for solving linear systems.

Abstract: Due to the extremely large size of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. Although IR drop analysis can be naturally formulated as the problem of solving a linear system, the system is too large to be solved by existing linear solvers. In this paper, we present two iterative algorithms based on node-by-node traversals and row-by-row traversals of the power grid, respectively. Our algorithms are extremely fast and guarantee convergence to the exact solutions. In fact, they can be considered as efficient implementations of the classical successive over relaxation iterative method for solving linear systems. Our methods take full advantage of the special structure of the power grid. Experimental results show that our algorithms out-perform the random-walk-based algorithm which is the best known method today. For a 16-million node problem, our row-based algorithm took 26.47 minutes while the random-walk-based algorithm took 19.6 hours. Our row-based algorithm produced an exact solution while the random walk produced a solution with maximum error of 5.7 mV.

105 citations

### "A clustering technique for fast ele..." refers background in this paper

...Recently, new reduction approaches have been proposed for electrical networks, based on the concept of node reduction [8]-[9]....

[...]

...In the following we assume that the grid discretization is fine enough that the branch lengths are smaller than or equal to the characteristic thermal length: in this case, we can adopt the same grid for the electrical and thermal problems [9]....

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14 Mar 2011

TL;DR: A block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis that is input-signal independent, different from those MOR schemes based on extended Krylov subspace technique, so the resulting ROM is reusable under different excitations.

Abstract: We propose a block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis. Compared with existing power grid model order reduction (MOR) methods, BDSM has several advantages. First, unlike many power grid reductions that are based on terminal reduction and thus error-prone, BDSM utilizes an exact column-by-column moment matching to provide higher numerical accuracy. Second, with similar accuracy and macromodel size, BDSM generates very sparse block-diagonal reduced-order models (ROMs) for massive-port systems at a lower cost, whereas traditional algorithms such as PRIMA produce full dense models inefficient for the subsequent simulation. Third, different from those MOR schemes based on extended Krylov subspace (EKS) technique, BDSM is input-signal independent, so the resulting ROM is reusable under different excitations. Finally, due to its blockdiagonal structure, the obtained ROM can be simulated very fast. The accuracy and efficiency of BDSM are verified by industrial power grid benchmarks.

19 citations