A column-based pixel-gain-adaptive CMOS image sensor for low-light-level imaging
09 Feb 2003-Vol. 103, Iss: 89, pp 224-490
TL;DR: In this article, a column amplifier and digital domain processing was used to reduce the fixed pattern noise to 55 /spl mu/V, and the saturation voltage was 1 V with a 2.5 V supply voltage.
Abstract: A 0.25 /spl mu/m technology CMOS image sensor employs a 4.2 /spl mu/m pitch pinned-photodiode pixel. A column amplifier and digital domain processing reduce the fixed pattern noise to 55 /spl mu/V. The saturation voltage is 1 V with a 2.5 V supply voltage, and the dynamic range is 69 dB.
Citations
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TL;DR: In this paper, the temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity.
Abstract: The temporal read noise on the signal path of a complementary metal-oxide semiconductor image sensor is analyzed to investigate the effectiveness of high-gain column amplifiers in enhancing sensor sensitivity. The signal path examined includes a pixel source follower, a switched-capacitor, noise-cancelling, high-gain amplifier, and a sample-and-hold circuit in each column. It is revealed that the total random readout noise consists of a component due to noise charge sampled and held at the charge summation node of the amplifier and transferred to the output, and a direct noise component sampled at the sample-and-hold stage at the output of the column amplifier. The analysis suggests that the direct noise components can be greatly reduced by increasing the column amplifier gain, indicating that an extremely low-noise readout circuit may be achievable through the development of a double-stage noise-cancelling architecture.
135Â citations
TL;DR: In this paper, a high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested, and the use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise.
Abstract: A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.
82Â citations
TL;DR: This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects and investigates their effects with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor.
Abstract: For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects In the CMS, the gain of the noise cancelling is controlled by the number of samplings It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises Two types of the CMS with simple integration and folding integration are proposed In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor Using 16 samplings, dynamic range of 594 dB and noise level of 19 e(-) for the simple integration CMS and 75 dB and 22 e(-) for the folding integration CMS, respectively, are obtained
64Â citations
TL;DR: A 3.9/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel has been developed for mobile applications as discussed by the authors.
Abstract: A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel has been developed for mobile applications. The newly developed CMOS pixel architecture realizes the minimum number of the transistors in one pixel. Small pixel size and sufficient fill factor are achieved by using the shared pixel architecture and floating diffusion driving. High conversion gain, low random noise, and low dark current are achieved by buried photodiode with complete charge transfer capability and correlated double sampling (CDS) circuit. The image sensor is fabricated in a thin planarized 0.35-/spl mu/m single poly-Si double-metal customized CMOS process in order to provide good image performance. The image sensor achieves low noise floor of 330 /spl mu/V and low dark current of 50 pA/cm/sup 2/ at 45/spl deg/C. This image sensor also realized various functions by on-chip digital and analog circuits.
53Â citations
13 Sep 2004
TL;DR: A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented, which achieves a 2.25/spl mu/m pixel pitch with 25% aperture ratio in a 0.
Abstract: A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented. This image achieves a 2.25/spl mu/m pixel pitch with 25% aperture ratio in a 0.25/spl mu/m IP2M CMOS process.
51Â citations
References
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07 Dec 1997
TL;DR: The first submicron pinned photodiode CMOS image sensors have been produced by adding an optimized image sensor module to a 33 V, 06 /spl mu/m CMOS process as mentioned in this paper.
Abstract: The world's first submicron pinned photodiode CMOS image sensors have been produced by adding an optimized image sensor module to a 33 V, 06 /spl mu/m CMOS process The 4-transistor pixel cells achieve excellent blue response, low dark current, and good dynamic range A full-color imager with good color reproduction has been produced using this technology
145Â citations
TL;DR: In this paper, a 256/spl times/256 pixel CMOS imager is described that exhibits 120 dB dynamic range, 56 dB signal-to-noise ratio (SNR), 65% fill factor, and an effective frame rate of 50 Hz.
Abstract: In this paper, a 256/spl times/256 pixel CMOS imager is described that exhibits 120 dB dynamic range, 56 dB signal-to-noise ratio (SNR), 65% fill factor, and an effective frame rate of 50 Hz. This has been achieved using a unique combination of a multiexposure and a multigain linear readout. The imager has been integrated in 1 /spl mu/m double-metal CMOS technology. The intended application is for driver's assistant systems, but the imager can be used for a wide range of applications requiring high dynamic range.
127Â citations
07 Feb 2000
TL;DR: In this paper, a hole accumulated diode (HAD) for sensing elements is applied to the CMOS image sensor, which consists of a 640/spl times/480 pixel array in 1/3 inch image format, a current-tovoltage converter, a correlated double sampling circuit and a timing generator.
Abstract: CMOS image sensors are generally characterized by their low power consumption, single power supply and capability for on-chip system integration in contrast with CCD image sensors. Even though CMOS image sensors have these advantages, they are not yet widely used in image capture applications because of their insufficient image quality due to the difficulty in FPN cancellation. This FPN-reduction technology and a hole accumulated diode (HAD) for sensing elements is applied to the CMOS image sensor. The CMOS image sensor consists of a 640/spl times/480 pixel array in 1/3 inch image format, a current-to-voltage converter, a correlated double sampling circuit and a timing generator. This image sensor uses a 0.35 /spl mu/m CMOS logic process with specialized add-on steps for HAD. The power supply is 3.3 V and maximum frame rate is 30 frames/s.
68Â citations
05 Dec 1999
TL;DR: In this paper, a low voltage buried photodiode for CMOS imager was developed to achieve high quality reproduced images comparable to CCD imager, which was operated in complete charge transfer mode at low voltage of 33 V.
Abstract: We have developed a low voltage buried photodiode for CMOS imager, in order to achieve high quality reproduced images comparable to CCD imager. The new buried photodiode has been operated in complete charge transfer mode at low voltage of 33 V, and the image lag and kTC noise of the photodiode have been suppressed.
33Â citations