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Transactions on Nanotechnology
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A Compact SPICE Model for Organic TFTs and
Applications to Logic Circuit Design
Antonio Valletta, Ahmet S. Demirkol, Giovanni Maira, Mattia Frasca Senior Member, IEEE,
Vincenzo Vinciguerra, Luigi G. Occhipinti, Luigi Fortuna, Fellow, IEEE, Luigi Mariucci,
and Guglielmo Fortunato
Abstract—This work introduces a compact DC model devel-
oped for Organic Thin Film Transistors (OTFTs) and its SPICE
implementation. The model relies on a modified version of the
Gradual Channel Approximation (GCA) that takes into account
the contact effects, occurring at non-ohmic metal/organic semi-
conductor junctions, modeling them as reverse biased Schottky
diodes. The model also comprises channel length modulation and
scalability of drain current with respect to channel length. To
show the suitability of the model, we used it to design an inverter
and a ring oscillator circuit. Furthermore, an experimental
validation of the OTFTs has been done at the level of the
single device as well as with a discrete-component setup based
on two OTFTs connected into an inverter configuration. The
experimental tests were based on OTFTs that use small molecules
in binder matrix as an active layer. The experimental data on
the fabricated devices have been found in good agreement with
SPICE simulation results, paving the way to the use of the model
and the device for the design of OTFT-based integrated circuits.
Index Terms—Organic thin film transistors (OTFTs), SPICE
modeling, flexible electronics.
I. INTRODUCTION
C
HARGE transport mechanisms in organic field-effect
transistors (OFETs) have been investigated since the late
eighties [1]. After more than a decade of interdisciplinary
research efforts to better understand the materials, processing,
and device architecture requirements, it is now possible to
satisfy both performance and reliability requirements needed
in product applications [2]. Flexible active matrix backplanes
based on solution-processed organic field-effect transistors on
low-temperature plastic substrates have been demonstrated [3],
and are now capable of driving thin film displays, based on
either liquid-crystal displays (LCD) or organic light-emitting
diodes (OLED), as well as large-area sensor arrays, such as
organic photodetectors (OPD) [4].
Progress has also been made in fabricating electronic cir-
cuits based on OFETs for applications in radio frequency
identification tagging (RFID) [5], chemical and biochemical
A. Valletta, L. Mariucci and G. Fortunato are with IMM-CNR, Roma, Italy.
M. Frasca and L. Fortuna are with DIEEI, University of Catania, Italy (e-
mail: mfrasca@diees.unict.it). A. S. Demirkol was with DIEEI, University of
Catania and is now with Institute of Electrical Engineering at the Technical
University of Dresden, Germany. G. Maira is with Department of Physics
and Chemistry, University of Palermo, Palermo, Italy. V. Vinciguerra is with
STMicroelectronics, Catania, Italy. L. G. Occhipinti is with University of
Cambridge, Electrical Engineering Division, Cambridge, UK.
Manuscript received ***; revised ****.
sensors [6], [7], and in developing new platforms for pro-
cessing logic data based on OFET devices and logic gates
[8]. In the meantime, the initial challenges in production of
high performance air-stable organic materials in gram scale
are now solved, as required for manufacturing OFET scalable
circuits and related products. It is now clear that state-of-the-
art p-type OFETs with suitable materials and device structures
can exhibit speed performance, stability and uniformity of
parameters over large-areas comparable to those of a Si Thin
Film Transistor. Although the performance and integration
scale of organic thin film transistor-based circuits are not
comparable with those achieved by silicon in VLSI/ULSI
CMOS technology, the possibility to design and simulate
analogue and digital circuits that can be fabricated on thin
and flexible substrates makes the corresponding technology
platforms very attractive.
Developing accurate models of OFET devices is of essential
importance in order to allow adapting standard design and
verification tools and use well-established design and simula-
tion techniques to approach more complex integrated organic
electronic circuits and systems, and predict their behavior prior
to prototype manufacturing and scale up. Also it is critical
to develop the equivalent circuit models for OFETs, in a
way they are simple enough to perform circuit simulations
at transistor-level transient mode in a relatively short time.
For that, it is also essential to develop simulation models
sufficiently accurate to capture the physical effects that govern
charge transport mechanisms occurring in such devices, a nd
translating them into suitable behavioral models for both DC
and transient analysis.
The first attempts to develop OFET compact device models
were focusing on the peculiar charge transport mechanisms
occurring in the channel made by an organic semiconductor
material, based on theories developed so far such as variable
range hopping [9], [10]. In more recent works the compact
models have been adapted to include the effect of non-ohmic
contacts, often occurring at the interface between source and
drain contacts with the organic semiconductor channel [11],
and the dependence of contact resistance on both the gate
voltage and charge trapping mechanisms in grain boundaries of
polycrystalline organic semiconductors, of particular relevance
in staggered transistor devices [12], when the gate length is
reduced in the attempt of improving the speed performance of
OFET-based logics [13].
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Another challenge to be faced with when developing models
of OFETs is the possibility to convert physical models into
SPICE-equivalent compact models. Whenever this is possi-
ble and accurate enough for representing the real behavior
of OFET devices in their different working regimes, the
equivalent compact model will inevitably result in a much
more efficient tool for simulation and faster design of circuits
at relatively high level of complexity, still making use of
standard approaches for circuit design and simulation [14].
In the field of TFTs, in fact, given the diversity of device
architectures, materials and fabrication technologies, creating
one compact device model fitting all possible options re-
mains an open challenge and the need of developing SPICE-
equivalent standard models while extracting parameters from
electrical device characterization is evident [15]. We note that
the existing circuit simulation software SmartSpice by Silvaco
Inc. includes an OTFT simulation model, which takes into
account contact effects by simply introducing “extrinsic” linear
resistances on the source and/or drain side of the device and
not Schottky diodes or other non-linear elements [16]. Unlike
this approach, we aim at explicitly accounting for non-ohmic
contact behavior.
In this work, we report an implementation in SPICE of a
compact DC model developed for Organic Thin Film Transis-
tors (OTFTs) and tested on devices that use small molecules
in a binder matrix as active organic semiconductor layer.
The compact model is highly accurate, yet founded on the
original Gradual Channel Approximation (GCA) theory for
a unified transistor model proposed by Shockley in 1952
[17], and includes contact effects of non-ohmic junctions,
as well as the effect of channel length scaling and gate
voltage, which allows working out the modulation of drain
current as a function of the device channel length for design
and simulation of high performance device architectures and
circuits. The experimental data are obtained from a consistent
set of fabricated p-type devices with different geometries [18],
adapted to represent the characteristics of OFET devices made
by given fabrication techniques. The simulation results are
then validated against experimental data in fair agreement
with each other. The approach is further extended by deriving
the DC characteristic of an inverter gate, and using it in the
simulation of a ring oscillator based on the same inverter. From
the evaluation of performance of these circuits, the proposed
model and approach are suitable now for use in standard
design kits to allow design of complex electronic circuits based
on a subset of the fabricated test structure devices.
II. DEVICE MANUFACTURING
P-channel OTFTs, with staggered top-gate configuration
(Fig. 1), were fabricated on heat-stabilized, low rough-
ness polyethylene-naphthalate PEN foils (TeonexrQ65FA,
125 µm thick) by using solution processed semiconductor and
dielectric. Patterning of the source and drain gold contacts,
deposited by evaporation, were made by standard optically
lithography and wet etching. A self-assembled monolayer
of pentafluorobenzene thiol (PFBT) was deposited by spin
coating on the metal contacts in order to improve the struc-
tural properties of organic layer [19] and carrier injection
Fig. 1. Section of the layout of the p-channel OTFT.
from the electrodes. Small-molecule organic semiconductor
(SmartKemrp-FLEX™, by SmartKem-Ltd, 30 nm thick)
and polymer gate dielectric (Cytop™, 550nm thick, relative
dielectric constant ∼ 2.1) were sequentially deposited by spin
coating. Finally, gate electrode (evaporated Al, 50 nm thick)
and device islands were photolithographically defined. All
curing steps were carried out below 100
◦
C to be compatible
with the PEN substrate. The OTFTs sizes were in the range
from 2 to 100 µm for channel length L, and 50, 100 and
200 µm for channel width W .
III. DC MODEL OF THE DEVICE
The electrical characteristics of OTFTs often show some
peculiarities that are not present in the characteristics of
conventional crystalline silicon MOSFETs and that are not
reproduced by the existing compact models. In particular, the
drain current obtained from the transfer characteristics at low
V
DS
of OTFTs, above the threshold regime, frequently has a
power law dependence on the gate voltage that differs from
the linear behavior predicted by the GCA of a conventional
MOSFET for a low drain-source voltage drop. The exponent
of the power law is often found greater than 1, giving the
transfer characteristics in above threshold a convex function
behavior that cannot be ascribed to series resistance effects
but has to be attributed to the intrinsic dependence of the
carrier mobility upon charge concentration in the organic
semiconductor [20]. On the other hand, often it is found that, in
below threshold regime, the transfer characteristics of OTFTs
have an exponential like behavior.
Moreover, the output characteristics of OTFTs often un-
dergo contact resistance effects that are related to the presence
of non-ohmic metal/organic semiconductor junctions. It is
found [13] that, in normal operation, the electrical behavior
of the metal/organic semiconductor on the source side of the
OTFT is similar to that of a reverse biased leaky Schottky
barrier junction. In addition, the reverse current is gate voltage
dependent [13]. The presence of such junction can appreciably
reduce the output current with respect to estimations made by
using the square-law behavior of the GCA theory. In fact, the
presence of a reverse biased Schottky junction at source side
of the device determines a voltage drop between the metal
contact and the organic semiconductor [12], [13], reducing
the effective gate-to-source and drain-to-source voltage seen
at the ends of the channel. Since the relevance of these
contact effects depends on the ratio between the contact
and channel resistance, their influence becomes progressively
more important as the channel length is scaled down [12],
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Fig. 2. Equivalent circuit representing the OTFT model.
[13]. Hence, it is very important to take into account these
effects in the development of a compact model that has to
be used to design circuits that employs short channel OTFTs.
Most of the OTFT models already proposed do not explicitly
account for contact effects [21], [22], [23], [24] or do it
in a phenomenological way [25]. A quite small number of
compact models that accounts for non-ohmic source and drain
contacts have already been proposed [26], [27]. Nevertheless
they often employ a somewhat non-physical modeling of the
metal/organic semiconductor interface. In fact, in [26] the
source junction is modeled as forward biased Schottky diode,
while it is commonly accepted that physically it is a reverse
biased junction, and in [27] a “contact” TFT is introduced,
while, in our paper, a gated diode is considered.
For these reasons we have developed a compact DC model
that can take into account non-linearity in the I
D
−V
GS
curves
as well as contact effects in the I
D
− V
DS
curves. The model
has been tested on experimental data of the OTFTs fabricated
as described in Sec. II.
The model illustrates a real OTFT as a serial combination
of an “ideal” OTFT which closely follows the GCA (M
0
in
Fig. 2), with a leaky reverse biased Schottky diode (D
0
in
Fig. 2) existing on source terminal side. Additionally, reverse
current of this diode depends on V
GS
and therefore we call it
as a gated diode. For convenience, the equations describing the
model were written with respect to n-type devices, but clearly
can be easily adapted to p-type devices.
Analogously to [20], we choose to model the current-voltage
relationship of M
0
as:
I
OT F T
= F (V
GC
) − F (V
GD
) + I
off
F (V ) = K
1
W
ef f
L
Early
V
SS
log
1 + e
V −V
F B
V
SS
m
I
off
= I
00
W
ef f
L
E arly
V
DC
L
Early
= L − dL
V ds
|V
DC
|
(1)
where K
1
is a prefactor dependent on the carrier mobility and
on the gate insulator capacitance per unit area; W
eff
is the
effective channel width of the OTFT; L is the geometrical (as
drawn) length of the channel; V
SS
is a parameter dependent
on the subthreshold slope of the transfer characteristics; V
DC
,
V
GC
and V
GD
are the potential drop between D, C and
G terminals (see Fig. 2); V
F B
is a voltage related to the
threshold voltage of the OTFT; I
off
is the off current; m
is an exponent related to the above threshold behavior of
the transfer characteristics; L
Early
is the channel effective
length due to drain bias modulation; dL
V
ds
is a parameter
determining the channel length modulation; and I
00
is the
off current prefactor. Since source and drain contacts are
symmetric, a metal/organic semiconductor junction is formed
also on the drain end of the channel: this has no impact on
the operation of the OTFTs since, in normal operation, the
resulting Schottky diode is polarized in forward bias, thus
determining only a small voltage drop on the drain junction
that has been neglected in our model. This is why in normal
operation (Fig. 2, left), we safely assume V
DB
= 0.
At this point, we note that the core function y = log(1 +
e
x
)
m
of Eqs. (1) behaves like y = x
m
(power law) for x > 0
and like y = e
mx
(exponential law) for x < 0, and, hence, is
able to model the transfer characteristics of the “ideal” OTFT
either above or below the subthreshold regime, with a single
analytical equation. Another advantage of Eqs. (1) is that it
automatically fulfill the GCA theory. In fact,if we neglect the
I
off
term, the underlying structure of (1) is
I
OT F T
= F (V
GC
) − F (V
GD
) (2)
and this is exactly the functional form that is obtained when
applying the GCA with F proportional to the integral of the
channel conductance. The various parameters used in Eqs. (1)
have been determined using an optimizing procedure on the
transfer and output characteristics of long channel devices, in
which contact effects are negligible.
The I-V relationship of the contact diode D
0
is modeled by
the following equations [13]:
I
rev
= I
00d
W
nom
max(V
GS
−V
gg0
,0)
V
∞
β
+
+
V
gmin
−V
gg0
V
∞
β
e
(
V
CD
V
diode
)
α
;
I
diode
= −I
rev
e
−
qV
CS
ηκT
− 1
(3)
where V
CS
(V
GS
) is the potential drop between C and S
(G and S) terminals; I
rev
is the diode reverse current which
depends on both V
CS
(Schottky effect) as well V
GS
(gated
diode); I
00d
is the diode reverse current prefactor; V
∞
= 1V
is a normalization coefficient; V
diode
and α are parameters
determining the I
rev
dependency upon V
CS
; β, V
gmin
and
V
gg0
are parameters determining the I
rev
dependency upon
V
GS
; η is the diode ideality factor; and q, κ and T have their
usual meanings: elementary charge, Boltzmann constant and
absolute temperature.
In Eqs. (3) the first term describes the power law depen-
dence of the reverse current upon the gate bias found in
OTFTs [13]. The exponential term, instead, represents the de-
pendence of I
rev
upon the potential drop on the metal/organic
semiconductor junction and takes into account the presence
of the Schottky barrier lowering effect [28]. The parameter
β is a strictly positive real number: while determining the
numerical value of the parameters, we impose the condition
that V
gmin
is strictly greater than V
g g0
. In this way the quantity
in square bracket in Eq. (3) is always strictly positive, because
of the presence of the max operator and the aforementioned
constraint on V
gmin
and V
gg0
.
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Fig. 3. SPICE equivalent implementation of the OTFT model.
As stated above, the presence of the reverse biased Schottky
diode in series to the source determines a potential drop
that reduces the effective gate bias (V
GC
) seen by M
0
, thus
reducing the output current. In this way, the saturation current
of short channel OTFT is affected by the saturation of D
0
.
It has to be pointed out that there is no explicit solution for
the potential of V
C
. Instead, it is computed by a software for
circuit simulation (e.g., Verilog-a) by solving the following
equality with respect to V
CS
:
I
diode
(V
CS
, V
GS
) = I
OT F T
(V
CS
, V
GS
, V
DS
) (4)
The parameters I
00d
, V
gg0
, V
gmin
, V
diode
, β and α used in
the diode equation [eq. (3)] have been determined by fitting
with Eq. (4) the transfer and output characteristics of short
channel devices, in which contact effects are prominent.
IV. SPICE IMPLEMENTATION
In order to define the p-OTFT model in SPICE we used
a behavioral approach, grouping several components into a
functional block. To implement Eqs. (1)-(3) we used voltage
controlled current sources (VCCS), as in Fig. 3. Using the
SPICE function “VALUE”, each current contribution is repre-
sented in the model as a different current source.
In Fig. 2 illustrating the DC model of the device, the
location of the Schottky diode in the device network as well
as the sign of the current passing through the channel of
M
0
, the “ideal” transistor (GCA), depends on the sign of
the potential drop between S and D nodes. In the SPICE
implementation of the model, we have considered that the
sign of V
DS
may change and, therefore, two gated diodes have
been included in the scheme of Fig. 3. The corresponding I-
V relationships (GDiodeS and GDiodeD in the SPICE model
of Fig. 4) are formulated in order to model a p-type OTFT:
the model is obtained from Eqs. (1)-(3), valid for a n-type
OTFT, by changing the signs of currents and potential drops.
The inversion of sign of the currents in the model is implicitly
obtained by reverting the order of the terminals appearing in
the current sources declarations with respect to the order in
which they would appear from a straightforward implemen-
tation of Eqs. (1)-(3). Likewise, the inversions of sign of the
voltage drops is implicitly obtained by reverting the order of
the terminals appearing in each of the voltage drop operators
of the model. The same approach was followed to express the
current contribution of M
0
. Depending on the sign of V
DS
,
one of the gated diodes of Fig. 3 is short circuited. This leads
to the fact that the voltage regulating the current contribution
Fig. 4. Code of the OTFT SPICE model.
of M
0
is in one case (V
DS
> 0) that on the terminals pd and
pc (d and c nodes) and in the other case (V
DS
< 0) that on
the terminals pb and ps (b and s nodes). These two cases are
implemented in SPICE by an “if” condition.
Differently from Fig. 2, the SPICE model needs additional
resistors in order to avoid convergence problems due to serially
connected dependent current sources. These resistors, with a
value of 100 GΩ, practically behave as an open circuit and do
not corrupt the drain current.
The complete SPICE model for the p-type OTFT, with all
parameter values included, is given in Fig. 4, where pc, pd,
pb, ps, pg correspond to C, D, B, S and G nodes of Fig. 3.
To show the accuracy of the SPICE model, we plot simulation
results and experimental data together in Figs. 5(a)-5(d) for a
long (L = 100 µm) and a short (L = 10 µm) channel device
(W = 200 µm in all cases). The supplied voltage is V
DD
=
50 V . We sweep V
SD
for a set of V
SG
in Figs. 5(a)-5(b) and
V
SG
for a set of V
SD
in Figs. 5(c)-5(d). Figs. 5(a)-5(d) clearly
show that the effect of the channel length modulation and the
scalability of the drain current are effectively accounted for in
the model. The compactness of the model allows the fabricated
devices to be efficiently simulated.
V. APPLICATION EXAMPLES
In this Section we discuss some application examples de-
signed using the SPICE model introduced in this paper. In
particular, we focus on an inverter and a ring oscillator. The
simplest inverter topologies using only one type of transistor,
p-type in our case, composed of only two transistors and
requiring a single voltage supply, still resulting in a reasonable
output in terms of gain and noise margin behavior, are the
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(a) (b)
(c) (d)
Fig. 5. Output characteristics I
SD
vs V
SD
and transfer characteristics I
SD
vs V
SG
for several OTFT with W = 200 µm and different L: (a) I
SD
vs
V
SD
for L = 100 µm ; (b) I
SD
vs V
SG
for L = 100 µm; (c) I
SD
vs V
SD
for L = 10 µm; (d) I
SD
vs V
SG
for L = 10 µm. Open circles represent
measured data, continuous line the model output.
diode loaded or current source loaded (CSL), also known as
zero V
GS
loaded, circuits [29], [30]. For the inverter design
employing depletion type transistors both for the driver and the
load transistor, it is more appropriate to use, rather than the
diode loaded one, a CSL type inverter, whose electrical scheme
is illustrated in Fig. 6(a). In this scheme, the load transistor
is connected in a zero source-gate configuration. Since all the
OTFTs are depletion type, the load transistor behaves as a
current source as long as it operates in saturation region. The
ratio of M
D
and M
L
sizes determines the location of the
trip (middle) point, the limits of high and low level, and the
sharpness (gain) of the VTC curve. In particular, to pull down
the output, the load transistor must be r times larger than
the load. For this reason we set this aspect ratio as r = 10
(W
D
= W
L
= 200 µm, L
D
= 100 µm, L
L
= 10 µm),
which is not an optimized value but corresponds to the sizes
of available OTFTs. For these OTFTs, we can use for our
simulations the parameter set calculated from the experimental
data.
The voltage transfer characteristics (VTC) as well as the
gain (derivative of VTC) curve are drawn in Fig. 6(b). Here,
the supply voltage ranges from 0 to 50 V and the input is swept
between these values as well. For the high level of input, the
output reaches 0 V although the opposite is not valid for the
low level of input. This typical situation of a CSL type inverter
can be improved by optimizing the ratio of load and driver
transistors. On the other hand, due to low output resistance of
the inverter, the gain is around 4. This is still an acceptable
(a) (b)
Fig. 6. (a) Topology of the CSL inverter. (b) Voltage transfer characteristics
(VTC) and gain of the inverter.
(a) (b)
Fig. 7. (a) Scheme of an inverter with a capacitive load. (b) Output of the
inverter for an ideal square wave input.
value for an OTFT based inverter circuit [31]. Moreover, we
also simulated the same topology with long channel devices
(L = 100 µm), sacrificing speed but increasing the output
resistance of the inverter, and obtained a gain of 20 which is a
very good value for OTFT based inverters [30]. Clearly, better
performances can be obtained using improved topologies with
a larger number of devices and external bias voltages [30]:
these topologies are beyond the scope of this paper.
To design the ring oscillator, all the device intrinsic and
parasitic capacitances are combined into an equivalent load
capacitance at the output node for simplicity (C
LOAD
in
Fig. 7(a)). The value of this capacitor (2pF ) results from a
(worst case) approximation [32] based on the geometry and
typical parameters [18] of the device. Under this assumption,
we simulate a single inverter excited by an ideal square wave,
and report the results in Fig. 7(b), where the input and output
waveforms of the inverter are shown. With a square wave input
of 12 .5 kHz frequency, the rise and fall behavior of the output
can be clearly observed.
The ring oscillator circuit (Fig. 8(a)) is designed with an odd
number of inverter stages. In particular, a chain of 11 inverters
has been used to obtain a square wave output with reasonable
low and high levels. The result of the SPICE simulations with
our OTFT model is given in Fig. 8(b). We obtain a low-to-high
propagation delay equal to τ
P LH
= 7.81 µs, and a high-to-low
propagation delay equal to τ
P HL
= 10.16 µs. The frequency
of operation is measured to be 4.82 kHz, a value in agreement
with the measured rise and fall times and number of stages.
Also note that, the high and low level of outputs agree with
Fig. 6(b). The frequency of oscillation may be increased by