A comparative analysis of jitter estimation techniques
01 Nov 2014-pp 125-130
TL;DR: This work describes both statistical domain methods and frequency domain methods for jitter estimation, which are based on fitting techniques and frequency spectrum analysis respectively.
Abstract: With the advancement of VLSI technology, the effect of jitter is becoming more critical on high speed signals. To negate the effect of jitter on these signals, the causes of jitter in a circuit need to be identified by decomposing the jitter. In this paper, a comparative analysis of various jitter estimation techniques is presented. The statistical domain methods are based on fitting techniques while the frequency domain methods are based on frequency spectrum analysis. This work describes both statistical domain methods and frequency domain methods. Further, their strengths and limitations are discussed. The algorithms are implemented in MATLAB and the results are extensively verified with Agilent ADS.
Citations
More filters
TL;DR: A novel jitter decomposition algorithm is proposed using convolutional neural networks to decompose random jitter and deterministic jitter by images of a jitter histogram, and predict the total jitter (TJ) at a BER of 10−12.
Abstract: Jitter is one of the crucial factors used to characterize high-speed serial links and integrated circuit performance. Jitter decomposition is key tool with which to characterize jitter at a given bit error rate (BER). In this article, a novel jitter decomposition algorithm is proposed using convolutional neural networks to decompose random jitter (RJ) and deterministic jitter (DJ) by images of a jitter histogram, and predict the total jitter (TJ) at a BER of 10−12. The jitter histogram – that is, training data – is obtained by modeling the high-speed serial link in an advanced design system. The test results verify the feasibility and accuracy of the proposed method. The RJ mean absolute error (MAE) of the test is 0.8721 ps and the error rate 6.74%, and the DJ MAE is 4.8684 ps and the error rate 2.03%, and TJ MAE is 8.9406 ps and the average error rate 2.13%. In addition, results show that the effectiveness of the proposed method is better than most other jitter decomposition methods by evaluating the average error rate.
11 citations
TL;DR: The previously reported algorithm to decompose duty cycle distortion as well as other deterministic jitter components including periodic jitter (PJ), intersymbol interference (ISI, and random jitter) is extended and described more detail with extensively simulation and measurements to verify the algorithm.
Abstract: In a high-speed digital communication system, jitter performance plays a crucial role in bit-error rate. It is important to accurately derive each type of jitter as well as total jitter and to identify root causes of jitter by jitter decomposition as a key tool. In this paper, we extend our previously reported algorithm to decompose duty cycle distortion as well as other deterministic jitter components including periodic jitter (PJ), intersymbol interference (ISI), and random jitter (RJ), and describe more detail of this algorithm with extensively simulation and measurements to verify the algorithm. The proposed ISI model only requires the time invariant condition, which is true for almost all systems, while the traditional ISI model is valid only with linear time invariant assumption. Compared to the conventional methods, the proposed jitter decomposition method is able to obtain estimated individual jitter component values with good accuracy by using fewer samples of total jitter data. The efficiency and accuracy of the proposed method were demonstrated by simulation and hardware experiments.
8 citations
TL;DR: A deterministic jitter decomposition method using Boolean output from a network of simple low-cost comparators to identify the deviation of current sampling position from the ideal sampling position instead of TIE data to reduce test cost greatly.
Abstract: Jitter decomposition is a key tool to identify root causes of jitters in a high-speed digital communication system. It is a huge challenge in balancing the test cost and precision for conventional decomposition methods implemented in instruments where the time interval error (TIE) data are necessary. In this paper, we propose a deterministic jitter decomposition method using Boolean output from a network of simple low-cost comparators to identify the deviation of current sampling position from the ideal sampling position instead of TIE data. The new method simultaneously separates intersymbol interference (ISI), periodic jitter (PJ), and duty cycle distortion (DCD). Simulation and measurement results demonstrate that the proposed method can estimate the ISI, PJ, and DCD with sufficient accuracy using significantly fewer data samples than the state-of-the-art instrument test, and thus, reduce test cost greatly. Furthermore, the comparators have extremely relaxed design requirements, offering potential for possible on-chip implementation for built-in self-test or background test.
7 citations
Cites methods from "A comparative analysis of jitter es..."
...In addition, it is more realistic than the first-order or second-order low-pass filter model [22], [23]....
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22 May 2016
TL;DR: A method for modeling the PLL with phase noise injection and estimating the time domain jitter is presented, which will help designers properly identify and quantify the sources of deterministic jitter and their impact on the SerDes system.
Abstract: Bit rates of high speed serial links (USB, SATA, PCI-express, etc.) have reached the multi-gigabits per second, and continue to increase. Two of the major electrical parameters used to characterize SerDes Integrated Circuit performance are the transmitted jitter at a given bit error rate (BER) and the receiver capacity to track jitter at a given BER. Modeling the phase noise of the different SerDes components, extracting the time jitter and decomposing it, would help designers to achieve desired Figure of Merit (FoM) for future SerDes versions. The phase locked loop (PLL) is one of the contributors of clock random and periodic jitter inside the system [1]. This paper presents a method for modeling the PLL with phase noise injection and estimating the time domain jitter. A time domain model including PLL loop nonlinearities is created in order to estimate jitter. The Standard Organizations specify random and deterministic jitter budgets. In order to decompose the PLL output jitter, a new technique for jitter analysis and decomposition is proposed. Modeling simulation results correlate well with measurements and this technique will help designers properly identify and quantify the sources of deterministic jitter and their impact on the SerDes system.
7 citations
Cites background from "A comparative analysis of jitter es..."
...Deterministic jitter (DJ) is predictable, the peakto-peak value of this jitter is bounded [3] [4]....
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TL;DR: This paper presents for the first time a novel method for generating the Gaussian distribution synthetic jitter patterns from colored-noise profiles for design verification and to achieve the desired figure of merit.
Abstract: Bit rates of high-speed serial links (USB, SATA, PCI-express, etc.) have reached the multigigabits per second, and continue to increase. The transmitted jitter at a given bit error rate is one of the key parameters used to describe the performances of a serializer/deserializer. Generating white- and colored-noise synthetic jitter patterns would allow to better analyze the effect of jitter in a system for design verification and to achieve the desired figure of merit. To our knowledge, there is no other method proposed in the literature to generate colored-noise patterns with the Gaussian distribution. This paper then presents for the first time a novel method for generating the Gaussian distribution synthetic jitter patterns from colored-noise profiles.
5 citations
Cites background from "A comparative analysis of jitter es..."
...Jitter contains random jitter (RJ), which is unpredictable, unbounded timing noise, and deterministic jitter (DJ), which is uncorrelated to the data and is bounded timing noise [2]–[8]....
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References
More filters
Book•
01 Jan 1989
TL;DR: In this paper, the authors provide a thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete time Fourier analysis.
Abstract: For senior/graduate-level courses in Discrete-Time Signal Processing. THE definitive, authoritative text on DSP -- ideal for those with an introductory-level knowledge of signals and systems. Written by prominent, DSP pioneers, it provides thorough treatment of the fundamental theorems and properties of discrete-time linear systems, filtering, sampling, and discrete-time Fourier Analysis. By focusing on the general and universal concepts in discrete-time signal processing, it remains vital and relevant to the new challenges arising in the field --without limiting itself to specific technologies with relatively short life spans.
10,388 citations
Book•
01 Jan 1999
1,700 citations
Book•
01 Mar 1993TL;DR: In this paper, the high speed properties of logic gates measurement techniques are discussed, including transmission lines, ground planes and layer stacking terminations, connectors, ribbon cables, clock distribution clock oscillators, etc.
Abstract: Fundamentals high speed properties of logic gates measurement techniques transmission lines ground planes and layer stacking terminations VIAS power systems connectors ribbon cables clock distribution clock oscillators.
639 citations
"A comparative analysis of jitter es..." refers background in this paper
...Inter-Symbol Interference (ISI) and Duty Cycle Distortion (DCD)are sub-components of DDJ. Reflection, discontinuities, limited bandwidth of the channel, threshold variation are the major root cause of DDJ [5] [6]....
[...]
Book•
19 Nov 2007
TL;DR: The fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes are introduced, and Dr. Li provides powerful new tools for solving these problems quickly, efficiently, and reliably.
Abstract: State-of-the-art JNB and SI Problem-Solving: Theory, Analysis, Methods, and ApplicationsJitter, noise, and bit error (JNB) and signal integrity (SI) have become today's greatest challenges in high-speed digital design. Now, there's a comprehensive and up-to-date guide to overcoming these challenges, direct from Dr. Mike Peng Li, cochair of the PCI Express jitter standard committee.One of the field's most respected experts, Li has brought together the latest theory, analysis, methods, and practical applications, demonstrating how to solve difficult JNB and SI problems in both link components and complete systems. Li introduces the fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes. He guides readers from basic math, statistics, circuit and system models all the way through final applications. Emphasizing clock and serial data communications applications, he covers JNB and SI simulation, modeling, diagnostics, debugging, compliance testing, and much more.Coverage includes? JNB component classification, interrelationships, measurement references, and transfer functions Statistical techniques and signal processing theory for quantitatively understanding and modeling JNB and related components Jitter, noise, and BER: physical/mathematical foundations and statistical signal processing views Jitter separation methods in statistical distribution, time, and frequency domains Clock jitter in detail: phase, period, and cycle-to-cycle jitter, and key interrelationships among them PLL jitter in clock generation and clock recovery Jitter, noise, and SI mechanisms in high-speed link systems Quantitative modeling and analysis for jitter, noise, and SI Testing requirements and methods for links and systems Emerging trends in high-speed JNB and SI As data rates continue to accelerate, engineers encounter increasingly complex JNB and SI problems. In Jitter, Noise, and Signal Integrity at High-Speed, Dr. Li provides powerful new tools for solving these problemsi??quickly, efficiently, and reliably.Preface xvAcknowledgements xxiAbout the Author xxiiiChapter 1: Introduction 1Chapter 2: Statistical Signal and Linear Theory for Jitter, Noise, and Signal Integrity 27Chapter 3: Source, Mechanism, and Math Model for Jitter and Noise 75Chapter 4: Jitter, Noise, BER (JNB), and Interrelationships 109Chapter 5: Jitter and Noise Separation and Analysis in Statistical Domain 131Chapter 6: Jitter and Noise Separation and Analysis in the Time and Frequency Domains 163Chapter 7: Clock Jitter 185Chapter 8: PLL Jitter and Transfer Function Analysis 209Chapter 9: Jitter and Signal Integrity Mechanisms for High-Speed Links 253Chapter 10: Modeling and Analysis for Jitter and Signaling Integrity for High-Speed Links 281Chapter 11: Testing and Analysis for Jitter and Signaling Integrity for High-Speed Links 309Chapter 12: Book Summary and Future Challenges 345Index 353
178 citations
"A comparative analysis of jitter es..." refers background in this paper
...The interpolation of data is used to simplify the process of obtaining DDJ....
[...]
...Inter-Symbol Interference (ISI) and Duty Cycle Distortion (DCD)are sub-components of DDJ. Reflection, discontinuities, limited bandwidth of the channel, threshold variation are the major root cause of DDJ [5] [6]....
[...]
28 Sep 1999
TL;DR: A new time-domain jitter separation method that automatically searches and fits the tail parts of the jitter histogram with nonlinear jitter models and estimates deterministic and random jitter components is presented.
Abstract: We present a new time-domain jitter separation method. Such a method automatically searches and fits the tail parts of the jitter histogram with nonlinear jitter models and estimates deterministic and random jitter components. Bit error rate (BER) calculation based on the deterministic and random jitter components is also discussed and demonstrated.
133 citations