A Comprehensive Computational Modeling Approach for AlGaN/GaN HEMTs
TL;DR: In this paper, the impact of surface and bulk traps on two-dimensional electron gas, device characteristics, and gate leakage is accounted for, and a new approach to accurately model the forward gate leakage in Schottky gate devices is proposed.
Abstract: This paper for the first time presents a comprehensive computational modeling approach for AlGaN/GaN high electron mobility transistors. Impact of the polarization charge at different material interfaces on the energy band profile as well as parasitic charge across the epitaxial stack is modeled and studied. Furthermore, impact of surface and bulk traps on two-dimensional electron gas, device characteristics, and gate leakage is accounted in this paper. For the first time, surface states modeled as donor type traps were correlated with gate leakage. Moreover, a new approach to accurately model the forward gate leakage in Schottky gate devices is proposed. Finally, impact of lattice and carrier heating is studied, while highlighting the relevance of carrier heating, lattice heating, and bulk traps over the device characteristics. In addition to this, modeling strategy for other critical aspects like parasitic charges, quantum effects, S/D Schottky contacts, and high field effects is presented.
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TL;DR: In this article, the design space for multifinger planar Schottky barrier diodes (SBDs) using AlN/GaN heterostructure for terahertz (THz) applications was explored.
Abstract: In this work, we have explored the design space for multifinger planar Schottky barrier diodes (SBDs) using AlN/GaN heterostructure for terahertz (THz) applications. Using a well-calibrated computational modeling framework, we have identified the critical design parameters and associated parasitic elements affecting diode’s THz performance. The 3-D modeling of parasitics components has been deployed as the 2-D design approach overestimates the performance or underestimates the parasitic components in a multifinger design. Device design guidelines and the tradeoff between various parameters are discussed in detail. The optimum design space and related tradeoffs were found to be nonintuitive due to the presence of 3-D parasitics capacitances and resistances.
3 citations
TL;DR: In this paper, GaN MOS capacitance?voltage device simulations considering various interface and bulk traps are performed in the transient mode, which explain various features of capacitancevoltage curves, such as plateau, hysteresis, and frequency dispersions.
Abstract: In this study, GaN MOS capacitance?voltage device simulations considering various interface and bulk traps are performed in the transient mode. The simulations explain various features of capacitance?voltage curves, such as plateau, hysteresis, and frequency dispersions, which are commonly observed in measurements of GaN MOS capacitors and arise from complicated combinations of interface and bulk deep-level traps. The objective of the present study is to provide a good theoretical tool to understand the physics of various nonideal measured curves.
3 citations
TL;DR: In this article , the authors proposed optimized field plate structures to improve the performance of AlGaN/GaN HEMT under electrical stress and achieved the highest off-state breakdown voltage (VBD) of 1188 V and 1120 V in the experiment, respectively, being 33 % and 25 % higher than that of NDFP-HEMT.
Abstract: We propose optimized field plate structures to improve the performance of AlGaN / GaN HEMT under electrical stress. The two structures are T-gate AlGaN / GaN HEMT with dual discrete field plates (DDFP-HEMT) and single discrete field-plate (SDFP-HEMT). Benefiting from the modulation effects of the field plate on the electric field, the DDFP-HEMT and SDFP-HEMT exhibit better breakdown characteristics and current collapse suppression. The performance of the two structure devices and no-discrete-field-plate devices (NDFP- HEMT) is explored in Silvaco TCAD. The DDFP-HEMT and SDFP-HEMT achieve the highest off-state breakdown voltage (VBD) of 1188 V and 1120 V in the experiment, respectively, being 33 % and 25 % higher than that of NDFP-HEMT, respectively. In particular, the current collapse in DDFP-HEMT and SDFP- HEMT is reduced by 24 % and 9 % under 200 V stress bias, respectively, when compared to NDFP-HEMT. The DDFP-HEMT shows greatest reliability improvement in the three samples.
3 citations
TL;DR: In this article , a design strategy for drain and gate connected field plates should be adopted while keeping in mind the interplay of various charge sources across AlGaN/GaN epi-stack, which governs the electric field distribution across HEMT.
Abstract: We have established that a design strategy for drain and gate connected field plates should be adopted while keeping in mind the interplay of various charge sources across AlGaN/GaN epi-stack, which governs the electric field distribution across HEMT. The investigations in this work are carried out for Schottky, MIS and p-GaN gate stacks while accounting for possible GaN buffer types (Fe-doped and C-doped). The role of gate and drain field plates was found to be different in the Fe-doped buffer compared to the C-doped buffer. More than suppression of avalanche generation, mitigation of gate injection by shifting the peak electric field position away from the gate edge was found to be the dominant cause of breakdown voltage improvement when field plates were adopted. In a few cases, however, the widening of the depletion region near the gate or dominance of the buffer field was the reason for breakdown voltage improvement with a gate field plate. On the other hand, the drain field plate was found to be effective only for lower polarization % and lower surface trap concentration. The role of buffer trap parameters, surface/passivation trap concentration, interface trap concentration at the gate, and passivation thickness in defining the optimum field plate strategy are discussed.
2 citations
01 Nov 2018
TL;DR: Differential conductance of submicron HEMT is analytically investigated as a function of drain bias for different structural parameters and parasitic effects in this article, where simulation is carried out for two different substrate based devices, Si and sapphire, and comparative study for those structural parameters at which V GS provides maximum transconductance.
Abstract: Differential conductance of submicron HEMT is analytically investigated as a function of drain bias for different structural parameters and parasitic effects. Simulation is carried out for two different substrate based devices, Si and sapphire, and comparative study is carried out for those structural parameters at which V GS provides maximum transconductance. Poisson's equation and carrier density equations are simultaneously solved to get drain current variations and parasitic effects are invoked through boundary conditions for realistic results. Result speaks that effect of threshold voltage is negligible on sapphire based device over a wider range of horizontal bias. Nanometric channel length provides almost constant conductance profile with insignificant magnitude.
2 citations
Cites background from "A Comprehensive Computational Model..."
..., [16] considered surface states as donor traps and calculated its effect on gate leakage current including different heating effects....
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References
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TL;DR: In this article, the authors investigated the role of spontaneous and piezoelectric polarization on the carrier confinement at GaN/AlGaN and AlGaN/GaN interfaces.
Abstract: Carrier concentration profiles of two-dimensional electron gases are investigated in wurtzite, Ga-face AlxGa1−xN/GaN/AlxGa1−xN and N-face GaN/AlxGa1−xN/GaN heterostructures used for the fabrication of field effect transistors. Analysis of the measured electron distributions in heterostructures with AlGaN barrier layers of different Al concentrations (0.15
2,581 citations
TL;DR: In this paper, a combination of high resolution x-ray diffraction, atomic force microscopy, Hall effect, and capacitance-voltage profiling measurements is used to calculate the polarization induced sheet charge bound at the AlGaN/GaN interfaces.
Abstract: Two dimensional electron gases in Al x Ga 12x N/GaN based heterostructures, suitable for high electron mobility transistors, are induced by strong polarization effects. The sheet carrier concentration and the confinement of the two dimensional electron gases located close to the AlGaN/GaN interface are sensitive to a large number of different physical properties such as polarity, alloy composition, strain, thickness, and doping of the AlGaN barrier. We have investigated these physical properties for undoped and silicon doped transistor structures by a combination of high resolution x-ray diffraction, atomic force microscopy, Hall effect, and capacitance‐voltage profiling measurements. The polarization induced sheet charge bound at the AlGaN/GaN interfaces was calculated from different sets of piezoelectric constants available in the literature. The sheet carrier concentration induced by polarization charges was determined
1,439 citations
TL;DR: In this paper, the origin of the two-dimensional electron gas (2DEG) in AlGaN/GaN heterostructure field effect transistors is examined theoretically and experimentally.
Abstract: The origin of the two-dimensional electron gas (2DEG) in AlGaN/GaN heterostructure field effect transistors is examined theoretically and experimentally. Based on an analysis of the electrostatics, surface states are identified as an important source of electrons. The role of the polarization-induced dipole is also clarified. Experimental Hall data for nominally undoped Al0.34Ga0.66N/GaN structures indicate that ∼1.65 eV surface donors are the actual source of the electrons in the 2DEG, which forms only when the barrier thickness exceeds 35 A.
1,015 citations
"A Comprehensive Computational Model..." refers background in this paper
...[24] suggested that polarization charges alone are not sufficient to explain 2DEG profile and proposed that sur-...
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TL;DR: In this paper, an analytical expression for the electron and hole mobility in silicon based on both experimental data and modified Brooks-Herring theory of mobility was derived, which allows one to obtain electron and holes mobility as a function of concentration up to \sim 10^{20} cm-3 in an extended and continuous temperature range (250-500 K) within ± 13 percent of the reported experimental values.
Abstract: An analytical expression has been derived for the electron and hole mobility in silicon based on both experimental data and modified Brooks-Herring theory of mobility. The resulting expression allows one to obtain electron and hole mobility as a function of concentration up to \sim 10^{20} cm-3in an extended and continuous temperature range (250-500 K) within ± 13 percent of the reported experimental values.
886 citations
Additional excerpts
...in [37] and Farahmand et al....
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TL;DR: In this paper, the authors reported the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's on the same wafer.
Abstract: Surface passivation of undoped AlGaN/CaN HEMT's reduces or eliminates the surface effects responsible for limiting both the RF current and breakdown voltages of the devices. Power measurements on a 2/spl times/125/spl times/0.5 /spl mu/m AlGaN/GaN sapphire based HEMT demonstrate an increase in 4 GHz saturated output power from 1.0 W/mm [36% peak power-added efficiency (PAE)] to 2.0 W/mm (46% peak PAE) with 15 V applied to the drain in each case. Breakdown measurement data show a 25% average increase in breakdown voltage for 0.5 /spl mu/m gate length HEMT's on the same wafer. Finally, 4 GHz power sweep data for a 2/spl times/75/spl times/0.4 /spl mu/m AlGaN/GaN HEMT on sapphire processed using the Si/sub 3/N/sub 4/ passivation layer produced 4.0 W/mm saturated output power at 41% PAE (25 V drain bias). This result represents the highest reported microwave power density for undoped sapphire substrated AlGaN/GaN HEMT's.
752 citations
"A Comprehensive Computational Model..." refers background in this paper
...Mitigation of RF dispersion [25], [26], drain and gate lag effects...
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