A custom reconfigurable power efficient FIR filter
18 Mar 2016-pp 1-4
TL;DR: This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm, which shows that the above architecture consumes less power than the traditional one.
Abstract: Power consumption is the most crucial point of designing any architecture. Till the date so many techniques have been discussed for realizing Digital filters more power efficient. This paper presents a Custom Reconfigurable Power efficient FIR filter which is based on multiplier less configuration using RAG-n algorithm. As multiplier takes the maximum area of any hardware and consumes the highest power so here in this design it is optimized using realizing the multiplier with the help of adder and shifter. FIR filter is symmetrical and has linear phase so stable and easy to implement and supports the number of DSP system. Power analysis shows that the above architecture consumes less power than the traditional one.
Citations
More filters
01 Dec 2018
TL;DR: An analysis of this research is presented by studying the design approach and proposed architectures by various researchers from the last 20 years in the branch of FIR filters with reconfigurable design.
Abstract: From the dawn of the VLSI based approach for the digital signal processing at most research is centered upon the digital filters and their designing, as filters are the circuit elements which are mainly used in signal processing where among these digital filters the group of filters that have finite duration of impulse response are called FIR(finite impulse response) filters and are having the preference over other groups of filters in the classification as their linearity and standard signal processing characteristics are conducive for implementing in microprocessors and DSP’s(digital signal processor). As the ever-changing reforms in technology take place, a system with reconfigurable design has to be provided in order to cope up with the transitions in the research timeline and since there have been many years of ongoing research in the branch of FIR filters with reconfigurable design an analysis of this research is presented by studying the design approach and proposed architectures by various researchers from the last 20 years.
1 citations
Cites methods from "A custom reconfigurable power effic..."
...A power efficient custom reconfigurable FIR filter [19]architecture is proposed with a multiplier replaced design and a multiplier was configured only using adder and shifter....
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01 Jan 2022
TL;DR: A review on some of the techniques of designing the FIR filter efficiently has been presented in this paper , where the authors mainly focused on the adaptive filter design techniques and their performance parameters like area, power consumption, speed and complexity.
Abstract: AbstractIn this paper, a review on some of the techniques of designing the FIR filter efficiently has been presented. Most of the Digital Signal Processing (DSP) devices use digital FIR filter due to its various advantages over IIR filter. In designing these filters, there are many performance parameters like area, power consumption, speed and complexity, which put challenges in front of a designer. In order to meet the desired performance, many techniques have been proposed. This paper is mainly focused on some of these techniques.KeywordsAdaptive filterDigital Signal Processing (DSP)Distributed Arithmetic (DA)FIR filterReconfigurable
References
More filters
TL;DR: Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Abstract: This paper describes a class of number representations which are called signed-digit representations. Signed-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers. Carry-propagation chains are eliminated by the use of redundant representations for the operands. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum (or difference) digit is the function only of the digits in two adjacent digital positions of the operands. The addition time for signed-digit numbers of any length is equal to the addition time for two digits. The paper discusses the properties of signed-digit representations and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff. A brief discussion of logical design problems for a signed-digit adder concludes the presentation.
1,232 citations
"A custom reconfigurable power effic..." refers background in this paper
...The technique used for graph representation [8] in single coefficient is superior than CSD.MAG-n algorithm [4] uses 12 bit coefficient for constant integer multiplication....
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...In Canonical signed digit (CSD) [2], signed digit limits the propagation of carry to the left side during the operations such as addition and subtraction....
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...Therefore, POF technique is advantageous than CSD....
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TL;DR: Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time.
Abstract: The computational complexity of VLSI digital filters using fixed point binary multiplier coefficients is normally dominated by the number of adders used in the implementation of the multipliers. It has been shown that using multiplier blocks to exploit redundancy across the coefficients results in significant reductions in complexity over methods using canonic signed-digit (CSD) representation, which in turn are less complex than standard binary representation. Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time. Significant savings in filter implementation cost over existing techniques result in all three cases. For a given wordlength, it was found that a threshold set size exists above which the multiplier block is extremely likely to be optimal. In this region, design computation time is substantially reduced. >
601 citations
"A custom reconfigurable power effic..." refers methods in this paper
...The RAG-n algorithm [3] is used to design a multiplier block in the best way for realizing the reconfigurable custom FIR block....
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01 Jun 1991
TL;DR: Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers.
Abstract: The authors outline a design methodology for the realisation of digital filtering structures with significantly reduced numbers of elementary arithmetic operations. The directed acyclic graphs which result from the design algorithms completely describe the filter arithmetically and may be mapped directly onto hardware or software realisations. Vertex rearrangement, retiming and edge elimination techniques are presented which facilitate the generation of a logical graph with an efficient allocation of pipeline registers. An example of the technique is given for a bit-serial realisation employing a bit-level pipeline. >
306 citations
"A custom reconfigurable power effic..." refers methods in this paper
...POF (Primitive Operator Digital filter) [1] design is done with the reduced number of arithmetic operation....
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...For fixed number coefficient FIR filters, the process used in [1] requires less adders compared to BH algorithm....
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...It is suggested in [1] that the multiplier block is irregular as in [6] is disadvantage for VLSI design....
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01 Oct 1994
TL;DR: A new method of formulating constant integer multiplication that requires fewer adders in general than a canonic signed-digit (CSD) representation is presented and an exhaustive search algorithm is described, and applied for word-lengths up to 12 bits.
Abstract: A new method of formulating constant integer multiplication is presented. It requires fewer adders in general than a canonic signed-digit (CSD) representation. Graphs are used to illustrate multiplier implementation. A general suboptimal algorithm for the design of multipliers of any wordlength is presented. For 32-bit words, it achieves an average improvement of 26.6% over CSD. Rules for the generation of graphs with the minimum number of adders and subtracters are presented. An exhaustive search algorithm using these rules is described, and applied for word-lengths up to 12 bits. For 12-bit words, it was found that an average improvement of 16% over CSD is achievable.
234 citations
"A custom reconfigurable power effic..." refers methods in this paper
...Secondly ,heuristics which uses tables of lookup [5] by other algorithms whose range is till 4096....
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01 Jan 2015
169 citations