Proceedings ArticleDOI
A delay model and speculative architecture for pipelined routers
Li-Shiuan Peh,William J. Dally +1 more
- pp 255-266
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This paper introduces a router delay model that accurately models key aspects of modern routers and introduces a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a brown hole router.Abstract:
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific flow control method employed the delay of the flow control credit path, and the sharing of crossbar ports across virtual channels. Motivated by this model, we introduce a microarchitecture for a speculative virtual-channel router that significantly reduces its router latency to that of a brown hole router. Simulations using our pipelined model give results that differ considerably from the commonly assumed 'unit-latency' model which is unreasonably optimistic. Using realistic pipeline models, we compare wormhole and virtual-channel flow control. Our results show that a speculative virtual-channel router has the same per-hop router latency as a wormhole router while improving throughput by up to 40%.read more
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References
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Book
Virtual-channel flow control
TL;DR: Simulation studies show that, given a fixed amount of buffer storage per link, virtual-channel flow control increases throughput by a factor of 3.5, approaching the capacity of the network.
Journal ArticleDOI
The Torus Routing Chip
TL;DR: The torus routing chip (TRC) is a selftimed chip that performs deadlock-free cut-through routing ink-aryn-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels.
Book
Digital Systems Engineering
William J. Dally,John W. Poulton +1 more
TL;DR: The techniques described in this book, which were once used only in supercomputers, are now essential to the correct and efficient operation of any type of digital system.
Book
Logical Effort: Designing Fast CMOS Circuits
TL;DR: In this article, the authors derived the method of logical effort from design examples and calculated the logical effort of gates, and then calibrated the model to achieve equal rising and falling delays.
Journal ArticleDOI
A cost and speed model for k-ary n-cube wormhole routers
TL;DR: A parameterized cost model for router performance, characterized by two numbers: router delay and flow control time, is described, which is used to compare a number of proposed routing algorithms.