A Design Approach for Server Power Supplies for Networking Applications
Laszlo Huber and Milan M. Jovanović
Delta Products Corporation
Power Electronics Laboratory
P.O. Box 12173
5101 Davis Drive
Research Triangle Park, NC 27709
Abstract - Present specifications for computer power supplies
for networking applications call for designs with dual inputs: the
universal ac-line input and the 48-V nominal dc input. In this
paper, a design and evaluation of the dc-input version of a 900-
W server power supply is presented. The dc-input version of
this power supply is leveraged from the ac-input version by
using the same output stage, and by replacing the ac front-end
in the ac-input version with a dc front end which provides the
same input voltage to the output stage. By adopting this design
approach, it is possible to achieve design modularity, design
standardization, minimize the design time, optimize utilization
of resources, and minimize the cost. The dc-input version uses a
cascade connection of two dc boost converters because of its
superior performance compared with other topologies.
I. INTRODUCTION
With a rapid growth of the Internet, telecom operators are
aggressively adding new equipment to their networks so that
they can use the existing telecom infrastructure to provide
Internet services. This new equipment consists primarily of
data processing and networking equipment such as servers,
routers, and modems. This collocation of the data and
telecom equipment has brought about new requirements for
powering data processing equipment [1].
Generally, the computer and telecommunication industries
employ different power system architectures because of
different requirements on their reliability and availability
performance, as well as reserve time in the case of an ac
outage. The telecom industry uses a -48-V-bus distributed
power system, which is backed up by a -48-V dc battery
plant. The battery plant usually provides many hours of
reserve time. The computer industry employs uninterruptible
power supplies (UPSs) to provide reserve time during
blackouts. Typically, an UPS system provides up to 30
minutes of the reserve time, which is by far much shorter than
the reserve time required by telecommunication systems. As
a result, powering of power supplies from the -48-V telecom
dc bus is a natural choice for data processing equipment
placed in the telecom environment. In fact, present
specifications for power supplies for computers for
networking applications already call for designs with dual
inputs: the universal ac-line input and the 48-V nominal dc
input.
The requirement for the dual input-voltage power supplies
puts a significant burden on the power supplies manufacturers
because of the additional efforts and resources necessary to
design, manufacture, and handle two versions of a power
supply. Furthermore, since presently the volume of the dc-
input version is still a small fraction of the volume of the ac-
input version, the additional engineering effort required for
the design of the dc-input version might not pay off, unless
the dc-input version design is done by leveraging the ac-input
version design to the highest extent possible.
To minimize the effort and resources required for the
design of a dual-input power supply for computers for
networking applications, a maximally leveraged, modular
design approach is proposed in this paper. In this approach,
the ac- and dc-input versions of the power supply use
different front ends and the same output stage, as shown in
Fig. 1. Specifically, the ac-input version employs a PFC
boost-converter front end, whereas the dc-input version uses
a cascade connection of two dc/dc boost converters. The
implementation with two cascaded boost converters was
selected because of its superior performance compared with
other topologies.
The proposed modular design does not require any
redesign of the output stage since both front ends provide the
same input voltage to the output stage, usually, 380 V. In
addition, by physically separating the front end and the output
380 V
dc
DC / DC
OUTPUT
STAGE
DC / DC
FRONT END
(b)
36-75
V
dc
3.3 V
5 V
12 V
24 V
dc
DC / DC
OUTPUT
STAGE
AC / DC
FRONT END
380 V
90-264
V
ac
(a)
3.3 V
5 V
12 V
24 V
Fig. 1 Block diagram of (a) ac-input version and (b) dc-input version o
f
computer power supplies for networking applications. Note that the dc/dc
output stage is the same in both versions.
stage by placing them on two separate printed circuit boards,
and by providing the necessary interface between the boards
through connectors, it is possible to achieve a modular
design. Finally, the designs for both the ac and dc boost front
ends can be standardized for a number of power levels. With
standardized front-end modules, the design effort for the
dual-input power supplies can be dramatically reduced.
The proposed modular approach with two cascaded dc/dc
boost converters is evaluated on the dc-input front end for a
900-W server power supply for networking applications.
II. T
OPOLOGY EVALUATION
Generally, the front-end in the dc-input version of
computer power supplies for networking applications can be
implemented as a single-stage or multi-stage converter as
illustrated in Fig. 2. Since the safety isolation is achieved in
the dc/dc output stage, the front end does not need to be
isolated.
A. Single-Stage Front End
The simplest single-stage topology for the dc-input front
end is the boost converter, shown in Fig. 3. Because of the
380-V output voltage, for boost switch Q
B
, 500-V MOSFETs
or IGBTs, and for boost diode D
B
, 500/600-V fast-recovery
diodes should be used. The maximum duty cycle, obtained at
the minimum input voltage of V
imin
= 36 V, is approximately
0.9. This large duty cycle results in a high current stress in
the boost switch. Therefore, a hard-switched single-stage
boost converter could be employed only at lower output
power levels, typically below 200-350 W, depending on the
number of MOSFETs connected in parallel. With a passive
snubber (e.g., [2]), the output power of the single-stage boost
converter can be increased up to 350-400 W, whereas with an
active soft-switching (e.g., [3]), the output power could be as
high as 400-450 W.
To further increase the output power level, lower-voltage-
rated MOSFETs should be used. Generally, the 150/200-V
MOSFETs have a significantly lower on-state resistance than
the 500-V MOSFETs. To achieve a lower voltage stress on
the boost switch, the high output voltage seen by the boost
switch in Fig. 3 has to be decreased through a transformer. A
possible topology is the full-bridge isolated boost converter
[4], shown in Fig. 4. Unfortunately, in this topology the
voltage stress on the secondary-side diodes is doubled. As a
result, less efficient 900/1000-V fast-recovery-type rectifiers
must be used for D
1
and D
2
in Fig. 4. Due to a very high
primary-side current at the minimum input voltage, the
parasitic inductances of the circuit have a profound effect on
the circuit’s performance. Generally, the leakage inductance
of the transformer as well as the parasitic inductances of the
primary-side current traces should be minimized to reduce the
ringing associated with these inductances.
B. Two-Stage Front End
The simplest two-stage topology for the dc-input front end
is the cascade connection of two boost converters as shown in
Fig. 5. If the intermediate voltage between the two boost
stages is selected in the range V
o1
= 100-125 V, then in the
first stage 150-200 V MOSFETs and 150-200 V Schottky
diodes can be employed. The Schottky diodes have two
significant advantages over the corresponding fast-recovery
380 V
dc
DC / DC
OUTPUT
STAGE
SECOND
DC / DC
CONVERTER
(b)
36-75
V
dc
MULTI-STAGE FRONT END
FIRST
DC / DC
CONVERTER
110 V
dc
3.3 V
5 V
12 V
24 V
380 V
dc
DC / DC
OUTPUT
STAGE
DC / DC
CONVERTER
(a)
36-75
V
dc
3.3 V
5 V
12 V
24 V
SINGLE-STAGE FRONT END
Fig. 2 Block diagram of dc-input version of computer power supplies for
networking applications with (a) single-stage front end and (b) multi-stage
front end.
C
o
V
o
Q
B
Load
L
F
L
B
D
B
+
V
i
C
F
Fig. 3 Basic boost converter
Load
Q
1
Q
2
Q
3
Q
4
D
1
D
2
C
F
C
o
L
B
L
F
+
V
i
V
o
1 : N
Fig. 4 Full-bridge isolated boost converter
V
o2
Q
1
Load
L
F
L
1
D
1
+
V
i
C
o1
C
F
C
o2
D
2
L
2
V
o1
Q
2
Fig. 5 Two cascaded boost converters
diodes: lower forward-voltage drop and no reverse recovery.
At the same time, the second boost stage can be implemented
as the corresponding PFC boost stage in the ac-input version.
A boost converter supplied from a 100-125-V dc power
source exhibits a similar efficiency as the corresponding PFC
boost converter supplied from a 100-125-V
rms
ac power
source (typically, above 95%). Depending on the maximum
output power level, two or three MOSFETs should be
connected in parallel in both boost stages. Both boost stages
can operate with hard switching. For improved performance,
the second boost stage can be implemented with soft
switching [2], [3].
At higher output power levels, typically above 1000-
1500 W at the output of the front end, a possible alternative
to paralleling of the MOSFETs is paralleling of the boost-
converter modules, especially in the first boost stage. The
paralleled modules can be interleaved, which significantly
reduces the current ripple, and, therefore, the size of the filter
at both the input and output of the converter. However, the
interleaving of converters requires a more complex control
circuit in order to achieve a good current sharing between the
paralleled converters.
Another possible two-stage topology for the dc-input front
end is the cascade connection of a dc/dc transformer as the
first stage and the basic boost converter as the second stage,
as shown in Fig. 6. The dc/dc transformer operates in open
loop, with a constant duty cycle of approximately 50%. If the
turns ratio of the transformer in Fig. 6 is selected as N = 5-
5.5, then 100-150-V MOSFETs can be employed for switches
Q
1
-Q
4
. For secondary-side rectifiers D
1
and D
2
, 900/1000-V
fast-recovery diodes should be used. Capacitor C
b
in Fig. 6 is
the blocking capacitor, which should be carefully selected
because of the large rms value of the primary-side current.
Inductor L
r
in Fig. 6 represents the equivalent series
inductance. Unfortunately, the dc/dc transformer stage in
Fig. 6 suffers from a significant drawback. Because
intermediate voltage V
o1
is not regulated, at light loads
voltage V
o1
can significantly increase above the level
determined by the product of the input voltage and the
transformer’s turns ratio. In fact, at light loads, inductor L
r
operates in the discontinuous conduction mode (DCM). The
initial value of the current through L
r
at the beginning of each
switching cycle is determined by the resonance between L
r
and the capacitance of rectifiers D
1
and D
2
. To reset the
current through L
r
at light loads, voltage V
o1
reflected to the
primary side of the transformer has to be larger than the input
voltage. At very light loads, the increase of voltage V
o1
can
become substantial. To limit this increase of V
o1
, the initial
value of the current through L
r
has to be reduced. This can be
achieved by increasing the value of L
r
, i.e., by adding an extra
inductor in series with the primary winding of the
transformer. However, a smaller initial value of the current
through L
r
will result in a larger peak value of the primary
current at full load. The problem of the uncontrolled increase
of the intermediate voltage at light loads can be fully
eliminated only by employing a more complex circuitry.
Generally, it can be concluded that the bridge-type
topologies in Figs. 4 and 6 are less attractive than the single–
or two-stage boost-converter topologies because they require
an extra transformer, more complex control with high-side
drivers, and must employ less-efficient and more-expensive
high-voltage fast-recovery rectifiers.
III. D
ESIGN OF TWO CASCADED BOOST CONVERTERS
The design of the dc-input front end with two cascaded
boost converters is illustrated on a 900-W server power
supply for networking applications. The front end is
designed for an input voltage range of V
i
= 40-75 V, output
voltage V
o2
= 375 V, output power range of 50-1200 W, and
hold-up time requirement of 8 msec at nominal input voltage
V
inom
= 48 V. It should be noted that the maximum output
power of the front end (1200 W) is obtained by assuming
75% efficiency of the output stage of the 900-W server power
supply.
A. Power Stage
In order to use 150-V power devices in the first boost
stage, intermediate voltage V
o1
in Fig. 5 should be designed to
be in the range 100 V to 120 V. As V
o1
increases, the
efficiency of the first boost stage decreases while the
efficiency of the second boost stage increases. Furthermore,
as V
o1
increases, the voltage stress on boost switch Q
1
and
boost diode D
1
increases. The optimal value of intermediate
voltage V
o1
should be found experimentally. For the first
design iteration, V
o1
= 110 V was chosen. The two boost
stages operate at the same switching frequency. Their
operation should be synchronized in order to minimize the
noise interaction between them. First, the design of the
second boost stage is presented.
1) Second Boost Stage: The second boost stage is designed
by leveraging the design of the corresponding PFC stage in
the ac-input version of the power supply, i.e., by employing
the same major components as in the corresponding PFC
stage in the ac-input version. The same switching frequency,
f
S
= 80 kHz, was selected.
Q
1
Q
2
Q
3
Q
4
D
1
D
2
C
F
L
F
+
V
i
C
b
Load
C
o2
L
B
V
o1
C
o1
V
o2
L
r
D
B
Q
B
1 : N
Fig. 6 Cascaded dc/dc transformer and boost converter
The maximum average input current of the second boost
converter is
A36.11
11096.0
1200
22
max2
max2
=
⋅
==
i
o
avei
V
P
I
η
,(1)
where 96.0
2
=
η
is the assumed efficiency of the second
boost stage. The duty cycle is obtained as
707.0
375
110
11
2
2
2
=−=−=
o
i
V
V
D .(2)
From (1) and (2), the maximum rms current of boost switch
Q
2
is
A55.9
2max2max2
== DII
aveirmsQ
,(3)
and the maximum average current of boost diode D
2
is
A33.3)1(
2max2max2
=−= DII
aveiaveD
.(4)
Using the experience from the corresponding PFC stage in
the ac-input version of the power supply, boost switch Q
2
is
implemented with two IRFP22N50A (500 V, 22 A, 0.23
Ω,
TO-247) power MOSFETs from IR connected in parallel, and
diode D
2
is implemented with a single hyperfast diode with
soft recovery characteristic RHRP3060 (30 A, 600 V, TO-
220) from Harris. A 69-mm x 4-mm aluminum plate of 7”
length with 10 fins (10 mm x 2 mm) is used as the heatsink.
The desired value of boost inductor L
2
is around 0.5 mH
[3]. Boost inductor L
2
is implemented with two toroidal
cores Kool M
µ 77071-A7 (Magnetics), each with 68 turns of
copper wire AWG16.
The maximum rms ripple current through the output filter
capacitor is obtained as
A17.5707.033.3293.003.8
22
max2
=⋅+⋅=
rmsCo
I .(5)
To handle this large ripple current, two paralleled aluminum
electrolytic capacitors of 470
µF/450 V (Nippon Chemi-Con)
are used. The two paralleled 470
µF/450 V capacitors also
satisfy the 8-msec hold-up time requirement:
secm44.17
2
max2
2
min2
2
nom2
2
=
⋅
−
⋅=
o
oo
oH
P
VV
CT ,(6)
where V
o2min
= 310 V is used as in the corresponding PFC
stage in the ac-input version. The actual hold-up time will be
even longer because of the stored energy in the intermediate
capacitor, C
o1
.
2) First Boost Stage: The maximum average input current
of the first boost converter is
A25.33
4096.094.0
1200
min121
max2
max1
=
⋅⋅
==
i
o
avei
V
P
I
ηη
,(7)
where 94.0
1
=
η
is the assumed efficiency of the first boost
stage. The variation of the duty cycle is from
318.0
110
75
11
1
max1
min1
=−=−=
o
i
V
V
D ,(8)
to
636.0
110
40
11
1
min1
max1
=−=−=
o
i
V
V
D .(9)
From (7) and (9), the maximum rms current of boost switch
Q
1
is
A5.26
max1max1max1
== DII
aveirmsQ
,(10)
and the maximum average current of boost diode D
1
is
A1.12)1(
max1max1max1
=−= DII
aveiaveD
.(11)
Boost switch Q
1
is implemented with three IRF3415
(150 V, 43 A, 0.042 Ω, TO-220) power MOSFETs from IR
connected in parallel, and diode D
1
is implemented with a
single center-tap Schottky rectifier 30CPQ150 (30 A, 150 V,
TO-247) from IR. A 69-mm x 4-mm aluminum plate of 7”
length with 10 fins (10 mm x 2 mm) is used as the heatsink.
Boost inductor L
1
is designed to achieve a ripple current
with an amplitude (∆i
L1
/2) equal to 5-10% of the maximum
average input current I
i1avemax
, i.e.,
max1
1
max1min1
1
%)2010(
avei
S
i
L
I
fL
DV
i ⋅==∆ K .(12)
From (7), (9), and (12), it follows that the range of L
1
is
H9648
k80)65.6325.3(
636.040
1
µ
K
K
=
⋅
⋅
=L .(13)
Boost inductor L
1
is implemented with two pairs of toroidal
cores Kool Mµ 77071-A7 (Magnetics), each pair with 23
turns of two strands of copper wire AWG14.
The maximum ripple current across the output filter
capacitor, C
o1
, is obtained as
A16636.01.12364.015.21
22
max1
=⋅+⋅=
rmsCo
I .(14)
To handle this large ripple current, three paralleled aluminum
electrolytic capacitors of 330 µF/160 V (Panasonic) and one
metallized polyester film capacitor of 47 µF/150 V (Vishay)
are used.
B. Control Circuit
Major issues of the control circuit design are the
synchronization between the two boost PWM controllers, the
voltage-mode control, and the employment of high-current
gate drives to drive the paralleled MOSFETs.
An oscillator based on the integrated timer 555 generates
the synchronization pulses and the ramp signal for the
voltage-mode control. The PWM controllers of the two boost
stages are built around the integrated controllers 3843. For
driving the paralleled MOSFETs, the integrated MOSFET
drivers 4420 are used.
The schematic of the control circuit is shown in Fig. 7.
C. Layout
Major issues of the layout design are the requirement for a
symmetrical layout of the paralleled MOSFETs and a proper
connection between the power-ground plane and the control-
ground plane.
IV. EXPERIMENTAL RESULTS
The measured performance of the two stand-alone boost
stages is presented first. Tables I and II show temperature,
voltage-stress, and efficiency measurements versus
intermediate voltage V
o1
at worst case (minimum input
voltage and maximum load). As can be seen, with increasing
voltage V
o1
, the efficiency of the first boost stage decreases
+15V
C
21
1
V
DD
Out
6
7
V
DD
Out
In
2
Gnd Gnd
45
IC
5
C
29
G
2a
S
2a
S
2b
G
2b
C
11
C
10
15V
R
19
8
RC
FB
V
ref
Gnd
IC
4
2
CS
6
4
Q
14
R
32
C
25
R
31
C
27
R
33
C
26
R
34
R
37
R
36
7
5
1
C
26
Out
3
C
28
R
35
V
o2
8
RC
FB
V
ref
Gnd
IC
2
2
CS
6
4
R
15
C
23
C
13
R
16
R
18
V
CC
1
C
15
Out
5
C
17
R
17
R
10
C
12
R
14
Q
11
R
11
8
V
cc
Gnd
1
Trig
7
5
6
Out
Ctrl
3
4
2
V
o1
1
V
DD
Out
6
7
8
V
DD
Out
In
2
Gnd Gnd
45
IC
3
Tresh
Disch
Reset
7
Q
12
Q
10
V
CC
Comp
Comp
3
R
13
R
12
C
14
Q
13
C
20
G
1b
S
1b
S
1c
G
1c
G
1a
S
1a
R
22
R
24
D
11
R
23
R
25 R
27
D
12
R
26
R
28
R
30
D
13
R
29
IC
1
8
C
32
C
30
C
31
R
38
R
40
D
14
R
39
R
41
R
43
D
15
R
42
C
22
+15V
7.5k
3k
1k
2.2k
4.7k
0.1u
2N
2222
2N
2222
2N
4403
555
0.1u
1n
0.1u
1k
2.4k
3843A
C
16
0.1u
47u
25V
1u
5.1k
230k
20n
150k
0.1u
0.1u
47u
25V
1u
47u
25V
1u
0.1u
0.1u
3k
3k
0
1N4148
5.1
1N4148
1N4148
0
5.1
0
3k
5.1
3k
3k
5.1
5.1
0
0
1N4148
1N4148
4420
4420
5.1k
760k
2.7n
7.5k270n
15n
100k
1.1k
1k
2.4k
0.1u
2N
2222
2N
2222
3843A
0.1u
C
18
2.7u
Fig. 7 Control circuit schematic