A digitally assisted baseband filter with 9MHz bandwidth and 0.3 dB IQ mismatch for a WLAN receiver chain
24 May 2009-pp 261-264
TL;DR: A fifth order opamp-RC filter in a 65nm digital CMOS process designed for a WLAN receiver chain and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements.
Abstract: We describe the design of a fifth order opamp-RC filter in a 65nm digital CMOS process. Designed for a WLAN receiver chain, the baseband filter has a bandwidth of 9MHz and features extensive use of digital hardware to correct for analog imperfections and thereby relaxing area and power requirements. Measurements show a 24 dB adjacent channel attenuation and an out-of-band IIP3 of 33 dBm. The complete filter consumes 9.5mA from a 1.3V supply and occupies an area of 0.46mm2.
Citations
More filters
31 Oct 2013
TL;DR: This paper presents a filtering ADC for the LTE standard, where a Delta-Sigma modulator (DSM) is merged into the channel-select filter (CSF) of the LTE radio receiver, which introduces an additional 2nd-order suppression of both quantization and thermal DSM noise.
Abstract: This paper presents a filtering ADC for the LTE standard, where a Delta-Sigma modulator (DSM) is merged into the channel-select filter (CSF) of the LTE radio receiver. The CSF introduces an additional 2nd-order suppression of both quantization and thermal DSM noise, while the CSF transfer function is essentially maintained. The 65 nm CMOS prototype is clocked at 288MHz with a 9MHz LTE bandwidth, and has an input-referred noise of 8.1 nV/√Hz, 12 dB gain, and an in/out-of-band IIP3 of 11.5/27 dBVrms, with a power consumption of 11.3mW, resulting in state-of-the-art figure-of-merits (FOMs) for filtering ADCs.
13 citations
Cites background from "A digitally assisted baseband filte..."
...This is a consequence of damping the 2 integrator [4] instead of the 1, which is more common....
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12 Nov 2012
TL;DR: A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation has a 0.4 dB passband ripple, reconfigurable bandwidth, automatic RC tuning, and IQ-mismatch correction.
Abstract: A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation is presented. It has a 0.4 dB passband ripple, reconfigurable bandwidth (4.75–34.75 MHz), automatic RC tuning, and IQ-mismatch correction. The noise power spectral density referred to the filter input is 3.8pA/√Hz at 90 % of the bandwidth. The output referred third order intercept point (OIP3) is 39.4 dBm for a two tone input at 47 MHz and 70 MHz. By digitally controlling the passive circuit elements of the filter, the frequency dependent gain and phase IQ mismatch can be reduced, resulting in a remaining gain error below 0.35 % and a maximum phase error of 0.23 degrees. After calibration, the IQ matching is sufficient for a mean receiver image-rejection ratio of more than 60 dB. The current consumption is 39 mA from a 1.2 V supply.
11 citations
Cites methods from "A digitally assisted baseband filte..."
...To reduce the input referred noise of the biquad section the second integrator is damped as opposed to the more conventional choice of damping the first integrator [10]....
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TL;DR: In this paper, a low-power MOS parametric integrator (MPI) was proposed for the design of wideband discrete time sigma-delta (ΣΔ) modulators.
Abstract: This paper proposes a new low-power MOS parametric integrator (MPI) for the design of wideband discrete time sigma-delta (ΣΔ) modulators. The MPI is implemented with MOS capacitors, which provide the required gain by switching from inversion in the sampling phase into depletion in the amplification phase. Analysis along with simulation results illustrate that MPI consumes very low power dissipation compared to the conventional active integrators with some negligible performance changes. To verify this, the MPI is used in two wideband ΣΔ modulators, one with 8-bit resolution and the other with 13-bit resolution with input bandwidth and sampling frequency of 12.5 and 200 MHz, respectively. The first one is a second order single stage ΣΔ modulator and the second one is a MASH 2-2 modulator, both implemented in 0.18-μm CMOS technology. Simulation results indicate that these modulators save a significant amount of power consumption when their second integrator is replaced by MPI.
9 citations
Dissertation•
01 Jan 2014
TL;DR: This dissertation contains an introduction to the field and five papers that focus on the continuous-time (CT) Delta-Sigma modulator (DSM) as ADC, where the DSM is merged into the channel select filter to suppress the noise from the DSM.
Abstract: The ever increasing data rates in wireless communication require analog to digital converters (ADCs) with greater requirements on speed and accuracy, while being power efficient to prolong battery life. This dissertation contains an introduction to the field and five papers that focus on the continuous-time (CT) Delta-Sigma modulator (DSM) as ADC. Paper I analyses the performance degradation of dynamic nonlinearity in the feedback DAC of the DSM, caused by Vth mismatch in the current-switching (differential) pair of a current-steering DAC. A model is developed to study return-to-zero (RZ) and non-return-to-zero (NRZ) feedback DACs, with and without data-weighted averaging (DWA), where an RZ DAC with DWA recovers the performance. Paper II and III presents a feedback scheme for improved robustness against variations in loop delay. An RZ pulse, centered in the clock period, is used in the innermost feedback path which has the highest sensitivity to loop delay, while NRZ pulses are adopted in the outer feedback paths to reduce the sensitivity to clock jitter and lower the integrator slew rate requirements. Furthermore, the otherwise obligatory loop delay compensation path (e.g. an additional DAC and adder) could be omitted to reduce hardware complexity. A discrete-time model of the feedback scheme confirms a negligible loss in performance. The 3rd-order CT DSM in 65nm CMOS with 9MHz LTE bandwidth achieves 69/71dB SNDR/SNR and consumes 7.5mW from a 1.2V supply. Measurements with OFDM signals verify an improved tolerance to blockers outside the signal band of the DSM. Paper IV and V present two filtering ADCs, where the DSM is merged into the channel select filter to suppress the noise from the DSM. The first and second prototypes provide a 2nd- and 3rd-order channel select filtering and improve the SNDR of the DSM by 14dB and 20dB, respectively, which in theory can be exploited to reduce the DSM power consumption by four to eight times. The first prototype has a 288MHz clock frequency, a 9MHz LTE bandwidth, a 2nd-order Butterworth filter response with 12dB gain, an input-referred noise of 8.1nV/sqrt(Hz), an in/out-of-band IIP3 of 11.5/27dBVrms, and a power consumption of 11.3mW. The second prototype is clocked at 576/288MHz with an 18.5/9MHz LTE bandwidth, a Chebyshev filter response with 26dB gain, a low input-referred noise of 5nV/sqrt(Hz), and an in/out-of-band IIP3 of -8.5/20dBVrms, with a power consumption of 7.9/5.4mW for 2xLTE20/LTE20 mode. The prototype was characterized for OFDM modulated blockers and essentially meets the cellular standard LTE Rel. 11. A delay, introduced by the feedback DAC, is compensated by adjusting the filter coefficients to restore the original Chebyshev filter function. Both prototypes have state-of-the-art power efficiency compared to other filtering ADCs and are comparable or better than a stand-alone filter. Furthermore, the filtering ADC provides both filtering and A/D conversion, which suggests that the A/D conversion is included in a power efficient manner, broadly speaking "for free". (Less)
7 citations
15 May 2011
TL;DR: An ultra-low power 6th-order 7MHz-to−20MHz tunable active-RC low-pass filter that utilizes an adaptive-biased pole-cancellation push-pull buffer to greatly reduce the power consumption and an adaptive bias circuit is proposed to cooperate with the Opamp to tolerate the PVT variations.
Abstract: This paper presents an ultra-low power 6th-order 7MHz-to−20MHz tunable active-RC low-pass filter. Due to the proposed highly power-efficient Opamp, the filter only consumes 0.47 mA power from 1.8 V supply voltage, corresponding to 3.86 pW/Hz/pole normalized power. The Opamp utilizes an adaptive-biased pole-cancellation push-pull buffer to greatly reduce the power consumption. An adaptive bias circuit is proposed to cooperate with the Opamp to tolerate the PVT variations. The filter achieves 20.9 dBm in-band IIP3, and 298 µVrms integrated input-referred noise. The chip is fabricated in a standard 0.18 µm CMOS process, and occupies 0.21 mm2 silicon area without ESD/pads.
6 citations
Cites background from "A digitally assisted baseband filte..."
...It consumes much less power than the conventional active-RC, Gm-C, as well as other topologies with the similar bandwidth and order [3-7]....
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...On the other hand, the traditional Opamp (operational amplifier)-based active-RC topology is widely used [4] [5]....
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References
More filters
TL;DR: In this article, a 5GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25/spl mu/m CMOS technology.
Abstract: A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.
204 citations
TL;DR: In this article, a single-sideband mixing technique for localoscillator signal generation avoids frequency pulling in IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz).
Abstract: A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz) achieves a receiver sensitivity of -5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of -29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18-/spl mu/m CMOS and operating from 1.8-V power supply, the design consumes 171 mW in receive mode and 135 mW in transmit mode while occupying less than 13 mm/sup 2/.
129 citations
"A digitally assisted baseband filte..." refers background in this paper
...Direct conversion has become the architecture of choice in many wireless transceivers due to the increased levels of integration possible (see for example [1] [2] [3] [4])....
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TL;DR: A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package, providing a complete 802.11a solution.
Abstract: A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm/sup 2/ and is packaged in a 48-pin LPCC package. The chip passes better than /spl plusmn/2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.
113 citations
07 Aug 2002
TL;DR: A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/.
Abstract: A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.
67 citations
"A digitally assisted baseband filte..." refers background in this paper
...Direct conversion has become the architecture of choice in many wireless transceivers due to the increased levels of integration possible (see for example [1] [2] [3] [4])....
[...]
TL;DR: A single-chip dual-band 5.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology with an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch.
Abstract: A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.
60 citations
"A digitally assisted baseband filte..." refers background in this paper
...Direct conversion has become the architecture of choice in many wireless transceivers due to the increased levels of integration possible (see for example [1] [2] [3] [4])....
[...]