A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing
28 Mar 2013-pp 414-415
TL;DR: A divider-less SIPLL with self-adjusted injection timing is presented, which achieves not only low phase noise, but also low power in a low-phase-noise sub-harmonically injection-locked PLL.
Abstract: A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1, 2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented.
Citations
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TL;DR: The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB.
Abstract: This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL (IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO (Replica) is placed in a TDC-less synthesizable ADFLL to provide continuous tracking of voltage and temperature variations. The other VCO (main) shares the control voltage with the replica VCO but is placed outside the loop and is injection-locked to lower its jitter and accurately set its frequency to the desired one. This approach avoids timing problems in the conventional ILPLL since the injection-locked VCO is placed outside the feedback loop. It also achieves a low power and a small area, due to the absence of a power hungry TDC and an area-consuming loop filter, while tracking any PVT variations. The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB. It also consumes an area of only 0.022 mm2 resulting in the best performance-area trade-off system presented up-to-date.
92 citations
Cites background from "A divider-less sub-harmonically inj..."
...Other work [5] tries to overcome the timing issue by using a combination of FLL, subsampling PLL (SSPLL) and injection locking or using a timing adjusted phase detector (PD) to re-time injection [6]....
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...a timing adjusted Phase Detector (PD) to re-time injection [6]....
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...The work in [3], [6], [15] has a better FoM compared to this work however it occupies more than 10 times the area of this work due to the additional circuitry required to calibrate the injection timing and the use of LC-VCO in [3], [6]....
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TL;DR: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltagetemperature (PVT)-calibration is presented.
Abstract: A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was $\text {0.06 mm}^{2}$ and total power consumption was 9.5 mW.
80 citations
Cites background or methods from "A divider-less sub-harmonically inj..."
...The phase-control loops of [16] and [17] used a timing-adjusted phase detector (PD)...
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...However, the architecture of [16] could suffer a trade-off between the dynamic range...
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TL;DR: This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset, by insertion of a digital-to-time converter in the reference path.
Abstract: Although multiplying delay-locked loops allow clock frequency multiplication with very low phase noise and jitter, their application has been so far limited to integer-N multiplication, and the achieved reference-spur performance has been typically limited by time offsets. This paper presents the first published multiplying delay-locked loop achieving fine fractional-N frequency resolution, and introduces an automatic cancellation of the phase detector offset. Both capabilities are enabled by insertion of a digital-to-time converter in the reference path. The proposed synthesizer, implemented in a standard 65 nm CMOS process, occupies a core area of 0.09 mm $^{2}$ , and generates a frequency ranging between 1.6 and 1.9 GHz with a 190 Hz resolution from a 50 MHz quartz-based reference oscillator. In fractional-N mode, the integrated RMS jitter, including random and deterministic components, is below 1.4 ps at 3 mW power consumption, leading to a jitter-power figure of merit of $-$ 232 dB. In integer-N mode, the circuit achieves RMS jitter of 0.47 ps at 2.4 mW power and figure of merit of $-$ 243 dB. Thanks to the adoption of the automatic offset cancellation, the reference-spur level is reduced from $-$ 32 to $-$ 55 dBc.
60 citations
Cites methods from "A divider-less sub-harmonically inj..."
...They entail either the realization of an additional feedback loop detecting the time offset and retiming the injected pulse [13], [24], [26]–[28], or the adoption of techniques aiming to decouple the feedback of the PLL loop from the reference injection (such as the dual-pulse oscillator in [14], [34], or the dual loop in [29])....
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TL;DR: A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.
Abstract: A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.
56 citations
TL;DR: This paper introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs) and captures the asymmetric nature of ILO's lock-in range, and the impact of frequency error on injection strength and phase noise performance.
Abstract: A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the proposed FTL continuously tunes the oscillator’s free-running frequency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO’s lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of $0.25\;\text{mm}^2$ . The prototype ILCM generates output clock in the range of 6.75–8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of $190\;\text{fs}_{\text{rms}}$ , while consuming 2.25 mW power. This translates to an excellent figure-of-merit (FoM) of $-251\;\text{dB}$ , which is the best reported high-frequency clock multiplier.
48 citations
Cites methods from "A divider-less sub-harmonically inj..."
...In [10] and [15], the injection timing is matched relying on a time-adjusted SS phase detector with high gain....
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...Compared to prior arts, which either rely on a complex power hungry architecture [13] or sensitive analog approaches [14], [15], the proposed FTL is based on a simple and accurate digital pulse gating technique that ensures robust operation across PVT variations....
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References
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TL;DR: A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon, which explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue.
Abstract: A complete analysis on subharmonically injection-locked PLLs develops fundamental theory for subharmonic locking phenomenon. It explains the noise shaping phenomenon, locking range and behavior, PVT tolerance, and pseudo locking issue. All of the analyses are verified by real chip measurements. Two 20-GHz PLLs based on the proposed theory are designed and fabricated in 90-nm CMOS technology to demonstrate the superiority and robustness of this technique. The first chip aims at low-noise/low-power/high-divide-ratio design, achieving 149-fs rms jitter (integrated from 100 Hz to 1 GHz) while consuming 38 mW from a 1.3-V supply. The second prototype shoots for the lowest noise performance, presenting 85-fs rms jitter (the same integration interval) with a power dissipation of 105 mW. The jitter generation (from 50 kHz to 80 MHz) measures 48 fs, which is at least twice as small as that of any other known circuits.
175 citations
"A divider-less sub-harmonically inj..." refers background in this paper
...In [3-5], a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented....
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...The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations [1-3,5]....
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TL;DR: A pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock using a mostly-digital feedback circuit that provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency.
Abstract: This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mum integrated circuit with active area of 0.4 mm2 and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), -63.9 dBc, and 200 fs (peak-to-peak), respectively.
101 citations
20 Dec 2012
TL;DR: A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion, but the sub-harmonically injection-locked technique, sub-sampling technique, and the multiplying delay- Locked loop (MDLL) can significantly improve the phase noise of aninteger-N PLL.
Abstract: A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion. The sub-harmonically injection-locked technique [1–3], sub-sampling technique [4], and the multiplying delay-locked loop (MDLL) [5–8] can significantly improve the phase noise of an integer-N PLL. In the sub-harmonically injection-locked technique, to inject a low-frequency reference clock into a high-frequency voltage-controlled oscillator (VCO), the injection timing should be tightly controlled [2–3]. If the injection timing varies due to process variation, it may cause a large reference spur or even cause the PLL to fails to lock [3]. In [1], a sub-harmonically injection-locked PLL (SILPLL) adopts a sub-sampling phase-detector (PD) [4] to automatically align the phase between the injection pulse and a VCO. However, a sub-sampling PD has a small capture range and a low bandwidth. The high-frequency non-linear effects of a sub-sampling PD may degrade the accuracy and limit the maximum speed of a VCO. In addition, a frequency-locked loop is needed for a sub-sampling PD. In [3], a delay line is manually adjusted to achieve the correct injection timing. However, the delay line is sensitive to process variations. Thus, the injection timing should be calibrated.
80 citations
"A divider-less sub-harmonically inj..." refers background in this paper
...In [3-5], a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented....
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...The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations [1-3,5]....
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...This conventional PLL is composed of a LC voltage-controlled oscillator (VCO) [5], a phase-frequency detector (PFD), a CP, a loop filter, and a divide-byN (=16) divider....
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07 Apr 2011
TL;DR: An injection-locked ring PLL (ILRPLL) architecture is proposed, using the concept of sub-sampling PLLs, where the injection window is aligned automatically without feedback adjustment, and a 432MHz ILRPLL is realized in ATV/DTV system to justify this technique.
Abstract: In modern analog front-ends, there is an increasing demand on high-performance analog-to-digital converters (ADCs), which require high sampling frequency and low-jitter sampling clock. This makes low-jitter phase-locked loops (PLLs) with jitter on the order of few picoseconds desirable. Unfortunately, due to stringent limit on die area, sometimes a PLL with a ring oscillator is the only choice. To get better phase noise, a wider loop bandwidth is needed to suppress the noise of the voltage-controlled oscillator (VCO). However, due to the discrete-time nature of the operations, the loop bandwidth is limited to one-tenth of the crystal oscillator (XTAL) frequency. One way to solve this problem is to use the injection-locking technique. This method exploits the clean reference clock but has several production problems. One is the frequency offset between injection signal and VCO, and this can be solved by using the injection-locked PLL architecture [1, 2]. However, in [1, 2] extra loops are still needed to adjust the injection window due to on-chip variations. In this work, an injection-locked ring PLL (ILRPLL) architecture is proposed to solve this problem. Using the concept of sub-sampling PLLs [3], the injection window is aligned automatically without feedback adjustment. A 432MHz ILRPLL is realized in ATV/DTV system to justify this technique.
66 citations
"A divider-less sub-harmonically inj..." refers background or methods in this paper
...In addition, the divider of a SIPLL [35] cannot be powered down to save the power as in [1,2]....
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...In [1,2], a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power....
[...]
...The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations [1-3,5]....
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TL;DR: In this paper, a novel circuit topology of a CMOS divide-by-4 direct injection-locked frequency divider is presented for millimeter-wave applications, where a series peaking technique is introduced in the proposed divider structure such that improved input injection efficiency can be achieved.
Abstract: In this paper, a novel circuit topology of a CMOS divide-by-4 direct injection-locked frequency divider is presented for millimeter-wave applications. To enhance the locking range for circuit operations with a division ratio of 4, a series peaking technique is introduced in the proposed divider structure such that improved input injection efficiency can be achieved. Using a standard 0.18-μm CMOS process, a V -band frequency divider is fabricated for demonstration. Operated at a supply voltage of 1.8 V, the divider core consumes a dc power of 12.6 mW. At an incident power of 0 dBm, the fabricated circuit exhibits an input locking range of 2.44 GHz in the vicinity of 60 GHz. The measured output power and locked phase noise at 1-MHz offset are -7 dBm and -133 dBc/Hz, respectively.
23 citations
"A divider-less sub-harmonically inj..." refers background in this paper
...It implies [6] that while a SIPLL is locked, the zero crossing of a VCO must occur at the pulse-width center of the injection pulse Inj_VCO....
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