A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology
TL;DR: In this article, a modular and power-scalable architecture for low-power programmable frequency dividers is presented, which consists of a 17-bit UHF divider, an 18-bit L-band divider and a 12-bit reference divider.
Abstract: A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.
Citations
More filters
IBM1
TL;DR: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented, which uses a gated-ring-oscillator time-to-digital converter to achieve integrated phase noise of less than 300 fs.
Abstract: A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancellation to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-mum CMOS process, the prototype occupies 0.95-mm2 active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is -108 and -150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.
325 citations
Additional excerpts
...For classical analog fractional-N synthesizers, it is common to use an asynchronous divider structure [14] due to its low power and compact layout....
[...]
Patent•
10 Feb 2005
TL;DR: In this paper, a fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards.
Abstract: A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.
249 citations
Book•
30 Apr 2003
TL;DR: The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results as discussed by the authors, which practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function.
Abstract: Radio frequency integrated circuits (RFICs) are the building blocks that enable every device from cable television sets to mobile telephones to transmit and receive signals and data. This newly revised and expanded edition of the 2003 Artech House classic, "Radio Frequency Integrated Circuit Design", serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function. This title is suitable for radio frequency integrated circuit (RFIC) design engineers; radio systems architects; researchers and developers of RFIC technology; and, graduate level electrical engineering students.
240 citations
01 Feb 2008
TL;DR: A digital fractional-N frequency synthesizer is presented that leverages a noise-shaping time-to-digital converter (TDC) and a simple quantization noise cancellation technique to achieve low phase noise with a wide PLL bandwidth of 500kHz.
Abstract: A digital fractional-N frequency synthesizer is presented that leverages a noise-shaping time-to-digital converter (TDC) and a simple quantization noise cancellation technique to achieve low phase noise with a wide PLL bandwidth of 500kHz. In contrast to previous cancellation techniques, this structure requires no analog components and is straightforward to implement with standard-cell digital logic.
233 citations
Additional excerpts
...For classical analog fractional-N synthesizers, it is common to use an asynchronous divider structure [14] due to its low power and compact layout....
[...]
TL;DR: In this article, a 2.4 GHz fully integrated /spl Sigma/spl Delta/ fractional-N frequency synthesizer in a 0.35-/spl mu/m CMOS process is presented.
Abstract: The design of a 2.4-GHz fully integrated /spl Sigma//spl Delta/ fractional-N frequency synthesizer in a 0.35-/spl mu/m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45/spl deg/-spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm/sup 2/ excluding the 0.5-mm/sup 2/ digital /spl Sigma//spl Delta/ modulator.
176 citations
Cites background from "A family of low-power truly modular..."
...Digital Object Identifier 10.1109/JSSC.2003.811875 Fig. 1. fractional- frequency synthesizer. power hungry [1]‐[ 6 ]....
[...]
References
More filters
05 Feb 1998
TL;DR: This dual-band CMOS receiver for GSM and DCS1800 applications incorporates hardware sharing between two paths to reduce the number of off-chip components.
Abstract: This dual-band CMOS receiver for GSM and DCS1800 applications incorporates hardware sharing between two paths to reduce the number of off-chip components. The receiver is an extension of the Weaver single-sideband architecture. The Weaver architecture performs two consecutive quadrature downconversion operations on the signal and the image such that if the final outputs are added, the signal is obtained and the image is suppressed and if they are subtracted, the reverse occurs. The fact that the addition or subtraction of the outputs in the Weaver architecture can select or reject two bands symmetrically located around a local oscillator (LO) frequency provides the foundation for the work reported here.
355 citations
01 Jan 1998
TL;DR: In this paper, a prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components.
Abstract: A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 /spl mu/s, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset.
291 citations
TL;DR: In this article, a dual-modulus divide-by-128/129 prescaler was developed in a 0.7-/spl mu/m CMOS technology, which enables the limitation of the high-speed section of the precaler to only one divideby-two flipflop.
Abstract: A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-/spl mu/m CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz.
282 citations
01 Jan 1998
TL;DR: In this article, a 4/sup th/order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components is presented.
Abstract: This design integrates a 4/sup th/ order type-2 charge-pump PLL frequency synthesizer for the DCS-1800 system in a standard 0.4 /spl mu/m CMOS process without external components. The VCO uses an integrated hollow planar inductor, formed in the 2 metal levels available on a lowly-doped substrate. The coil has a symmetrical octagonal shape and size optimized using 2-D circular finite-element analysis. Skin effect and eddy current losses are minimized, and the quality factor is 8.6. VCO phase noise is -122.5 dBc/Hz at 600 kHz offset and tuning range is 20%.
264 citations
NEC1
TL;DR: An adaptive pipeline (APL) technique is described, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations, and it is shown that MOS current-mode logic circuits are suitable for a low-noise variable delay circuit.
Abstract: This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.
146 citations