A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures
TL;DR: This work demonstrates a TaO(x)-based asymmetric passive switching device with which it was able to localize resistance switching and satisfy all aforementioned requirements, and eliminates any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
Abstract: Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.
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TL;DR: The performance requirements for computing with memristive devices are examined and how the outstanding challenges could be met are examined.
Abstract: Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.
3,037 citations
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TL;DR: The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide resistive switching random access memory (RRAM) are discussed, with a focus on the use of RRAM for nonvolatile memory application.
Abstract: In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.
2,295 citations
18 Jun 2016
TL;DR: This work proposes a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory, and distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving.
Abstract: Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.
1,197 citations
Cites background from "A fast, high-endurance and scalable..."
...The reported endurance of ReRAM is up to 10(12) [21], [22], making the lifetime issue of ReRAM-based memory less concerned than PCM based main memory whose endurance has been assumed between 10(6)-10(8) [23]....
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01 Jun 2018
TL;DR: This Review Article examines the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, theirresistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation.
Abstract: Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.
1,193 citations
TL;DR: A comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) can be found in this article, where a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMS over the past decade.
Abstract: This review article attempts to provide a comprehensive review of the recent progress in the so-called resistive random access memories (RRAMs) First, a brief introduction is presented to describe the construction and development of RRAMs, their potential for broad applications in the fields of nonvolatile memory, unconventional computing and logic devices, and the focus of research concerning RRAMs over the past decade Second, both inorganic and organic materials used in RRAMs are summarized, and their respective advantages and shortcomings are discussed Third, the important switching mechanisms are discussed in depth and are classified into ion migration, charge trapping/de-trapping, thermochemical reaction, exclusive mechanisms in inorganics, and exclusive mechanisms in organics Fourth, attention is given to the application of RRAMs for data storage, including their current performance, methods for performance enhancement, sneak-path issue and possible solutions, and demonstrations of 2-D and 3-D crossbar arrays Fifth, prospective applications of RRAMs in unconventional computing, as well as logic devices and multi-functionalization of RRAMs, are comprehensively summarized and thoroughly discussed The present review article ends with a short discussion concerning the challenges and future prospects of the RRAMs
1,129 citations
References
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TL;DR: This work has focused on defining just the storage node portion of the devices, which utilize the resis-tance change within the film to store information via two dif-ferent stable resistance states, and has attempted to de-termine the properties of such structures.
Abstract: while still retaining a selective switch (transistor or diode) asthe data storage element. Thus for high-density applications,crossbar structures are ideal, whereas for non-volatility, resis-tance-change materials showthe best promise. In orderto rea-lize the fabrication of universal memory elements, it is im-perative to develop a class of materials and structures thatcombine robust processibility, strong scalability, and rapidprogramming speed with non-volatility and low power con-sumption. In our work, we have focused on defining just thestorage node portion of the devices, which utilize the resis-tance change within the film to store information via two dif-ferent stable resistance states. Here, we have attempted to de-termine the properties of such structures and to study themechanisms behind resistance RAM (RRAM) storage. OurTi-doped (0.1 wt %) NiO samples deposited at room temper-ature show favorable node characteristics such as the lowestwrite current reported thus far for a unipolar switching resis-tance-change-based device (ca. 10 lA). In addition, the pro-gramming speed is comparable to the write time of SRAM(10 ns). By combining this node element with an appropriateselect switch, such as a high-performance diode, a thresholddevice, or a two-terminal non-ohmic device, it becomes possi-ble to fabricate high-density universal memory.Indeed, the fabrication of universal memory as the nextgeneration of non-volatile memory is the logical goal for re-search in this field. In comparison to Flash and dynamicRAM (DRAM), which are the current industry standards,next generation memories must combine the non-volatility ofFlash with the high-speed performance of SRAM.
166 citations
TL;DR: In this article, a perpendicularly magnetized spin-polarizing layer and a magnetic tunnel junction were used for OST-MRAM devices that incorporate an in-plane magnetized free layer and synthetic antiferromagnetic reference layer.
Abstract: Orthogonal spin-transfer magnetic random access memory (OST-MRAM) uses a spin-polarizing layer magnetized perpendicularly to a free layer to achieve large spin-transfer torques and ultrafast energy efficient switching. We have fabricated and studied OST-MRAM devices that incorporate a perpendicularly magnetized spin-polarizing layer and a magnetic tunnel junction, which consists of an in-plane magnetized free layer and synthetic antiferromagnetic reference layer. Reliable switching is observed at room temperature with 0.7 V amplitude pulses of 500 ps duration. The switching is bipolar, occurring for positive and negative polarity pulses, consistent with a precessional reversal mechanism, and requires an energy of less than 450 fJ.
156 citations
10 Jul 2009
TL;DR: In this paper, the relationship between the conducting filament resistance and reset voltage during the resistance switching of TiO2 thin films was examined assuming a filament with a conical shape, and it was shown that maintaining a higher set state resistance was more beneficial in achieving a more uniform reset voltage.
Abstract: This study examined the relationship between the conducting filament resistance and reset voltage during the resistance switching of TiO2 thin films assuming a filament with a conical shape. There was a critical resistance (∼20 Ω) of the set state above and below which the filament responded differently in response to the current. Maintaining a higher set state resistance was more beneficial in achieving a more uniform reset voltage. This filament model coincides well with the localized switching behavior and the recently microscopically observed filament shape.
141 citations
TL;DR: In this paper, the relationship between the conducting filament resistance and reset voltage during the resistance switching of TiO2 thin films was examined assuming a filament with a conical shape, and it was shown that maintaining a higher set state resistance was more beneficial in achieving a more uniform reset voltage.
Abstract: This study examined the relationship between the conducting filament resistance and reset voltage during the resistance switching of TiO2 thin films assuming a filament with a conical shape. There was a critical resistance (∼20 Ω) of the set state above and below which the filament responded differently in response to the current. Maintaining a higher set state resistance was more beneficial in achieving a more uniform reset voltage. This filament model coincides well with the localized switching behavior and the recently microscopically observed filament shape.
141 citations
Journal Article•
127 citations