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Proceedings ArticleDOI

A fast monolithic active pixel sensor with pixel-level reset noise suppression and binary outputs for charged particle detection

16 Oct 2004-pp 702-706
TL;DR: In this article, a pixel architecture with DC and AC coupling to charge sensing element was proposed, where in-pixel amplification is implemented together with double sampling, and hits from conversion of /sup 55/Fe photons were registered for the DC-coupled pixel.
Abstract: In order to develop precision vertex detectors for the future linear collider, fast monolithic active pixel sensors are studied. Standard CMOS 0.25 /spl mu/m digital process is used to design a test chip which includes different pixel types, column-level discriminators and a digital control part. In-pixel amplification is implemented together with double sampling. Different charge-to-voltage conversion factors were obtained using amplifiers with different gains or diode sizes. Pixel architectures with DC and AC coupling to charge sensing element were proposed. As far, hits from conversion of /sup 55/Fe photons were registered for the DC-coupled pixel. Double sampling is functional and allows almost a complete cancellation of fixed pattern noise.

Summary (2 min read)

Introduction

  • Precision vertex measurements will be a step forward.
  • Improvements in the spatial resolution are requested making the use of Active Pixel Sensors (APS) an attractive alternative to Hybrid Pixel Sensors (HPS), chosen for the forthcoming Large Hadron Collider (LHC) experiments, both in terms of electronic/detector integration and material thickness.
  • These sensors are designed with standard CMOS technology and have significant advantages over Charge Coupled Devices (CCDs).
  • The CDS processing implemented in-pixel is required to suppress the reset noise and pixel-to-pixel offset non-uniformities.

A. DC-Coupling Pixel Design

  • The pixel design with DC-coupling of the amplifier to the charge sensing diode is the basis of the chip design described in this paper.
  • The short interval between readouts in this application give us the opportunity to store easily the reset level of the detector in the pixel.
  • The voltage VRD, sampled by the readout circuitry during the RD phase, is the signal which also comprises the offset of the SF stage.
  • This pixel achieves high CVF using only 8 transistors in the pixel.
  • The DC current bias of the amplifier is determined by the voltage across the charge collecting diode.

B. Optional AC-Coupling Pixel Design

  • The pixel design with the direct AC-coupling of the amplifier to the charge sensing diode was used as a test structure for the current chip design.
  • The CDS circuitry is similar to that used in the DC-coupled pixel version.
  • The charge sensitive element is a two diode system, with an n-well/p-epi diode, collecting the charge available after particle impact, and a pplus/n-well diode, providing a constant reverse bias of the first one.
  • The signal of the charge sensitive element is delivered to the amplifier via the series capacitance obtained by placing the polysilicon plate over the n-well area, as it is shown in Fig. 2b.
  • The reference level for each new measurement is the state from the previous readout cycle.

III. ARCHITECTURE OF THE CHIP

  • A test chip was designed using a 0.25 µm CMOS digital process available through MOSIS.
  • The first array from the top of the chip is built with the AC-coupling pixel type.
  • The first 24 columns are connected to discriminators, multiplexed onto 4 outputs.
  • These direct outputs were used for testing of pixels with the results presented in the latter part of the paper.
  • The architecture was modified to use MOS capacitors instead poly-poly linear capacitors, because the fabrication process used does not feature this type of capacitors.

IV. TEST RESULTS

  • Two kinds of measurements were performed on the chip.
  • At the first step, the analog outputs were tested with a digital oscilloscope.
  • It was possible to observe the signal of one single pixel in this way.
  • The tests of the matrix containing pixels with AC coupling were also started.
  • The calibration is done, assuming that maximum signal observed for the exposition time correspond to the events of the photon impacts with conversion taking place in the n-well volume or in the depletion zone of the charge collecting diode, where the full quantity of the generated charge is collected within one pixel.

V. CONCLUSIONS

  • The new method with series connection of the clamped capacitance used in the pixel design for double sampling enables the offset of each pixel to be literally eliminated.
  • Taking into account the temporal noise level and the residual FPN, the detection of MIPs should be possible using this technique.
  • The small value of the residual pixel-to-pixel DC-level variation paves the way to the efficient on fly discrimination of signal during the readout of the detector, leading to the on-line data sparsification.
  • The next step for the characterization of the chip will be to make statistical measurements on analog and binary outputs using a fast data acquisition system currently under development.

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A fast monolithic active pixel sensor with pixel level
reset noise suppression and binary outputs for charged
particle detection
Y. Degerli, G. Deptuch, N. Fourches, A. Himmi, Y. Li, P. Lutz, F. Orsini
To cite this version:
Y. Degerli, G. Deptuch, N. Fourches, A. Himmi, Y. Li, et al.. A fast monolithic active pixel sensor
with pixel level reset noise suppression and binary outputs for charged particle detection. 2004 IEEE
Nuclear Science Symposium and medical imaging conference (NSS/MIC), Oct 2004, Rome, Italy.
�in2p3-00023818�

Abstract—In order to develop precision vertex detectors for the
future linear collider, fast active monolithic active pixel sensors
are studied. Standard CMOS 0.25 µm digital process is used to
design a test chip which includes different pixel types, column-
level discriminators and a digital control part. In-pixel
amplification is implemented together with double sampling.
Different charge-to-voltage conversion factors were obtained
using amplifiers with different gains or diode sizes. Pixel
architectures with DC and AC coupling to charge sensing element
were proposed. As far, hits from conversion of
55
Fe photons were
registered for the DC-coupled pixel. Double sampling is
functional and allows almost a complete cancellation of fixed
pattern noise.
I. INTRODUCTION
N the next generation of linear colliders required for
future high energy physics experiments, such as the Next
Linear Collider (NLC), the Japanese Linear Collider (JLC) and
the TeV Energy Superconducting Linear Accelerator
(TESLA), precise vertex detectors will be necessary to study
the Higgs mechanism. Secondary vertex measurements make
a high-resolution vertex detector a necessary part of the
detecting system. Precision vertex measurements will be a step
forward. Improvements in the spatial resolution are requested
making the use of Active Pixel Sensors (APS) an attractive
alternative to Hybrid Pixel Sensors (HPS), chosen for the
forthcoming Large Hadron Collider (LHC) experiments, both
in terms of electronic/detector integration and material
thickness. Precision vertex measurements will be a
requirement. There has been significant progress done by the
IReS/LEPSI-Strasbourg group in the use of the monolithic
active pixel sensors (MAPS) for the detection of Minimum
Ionizing Particles (MIP) [1]. An array of active sensors with a
Y. Değerli, N. Fourches, Y. Li, P. Lutz, and F. Orsini are with CEA Saclay,
DAPNIA/SEDI and SPP, 91191 Gif-sur-Yvette Cedex, France (e-mail:
{degerli, fourches, yanli, lutz, orsini}@hep.saclay.cea.fr).
G. Deptuch and A. Himmi are with LEPSI and IReS/IN2P3, 23 rue du
Loess, 67037 Strasbourg Cedex 02, France (e-mail: {deptuch,
himmi}@lepsi.in2p3.fr).
readout circuitry is integrated in a monolithic structure of a
silicon chip. These sensors are designed with standard CMOS
technology and have significant advantages over Charge
Coupled Devices (CCDs). Two exemplary strong points of
MAPS are the high radiation hardness and the flexibility of the
readout architecture design. In this paper the chip design with
new all-NMOS pixel architectures with integrated correlated
double sampling (CDS), suitable for charged particle detection
is presented.
PWR_ON
RST1
Pixel
Vr1
V
DD
Ib
n-well
p-epi
RST2
CS
MOSCAP
SF
Vr2
RD
CALIB
Column
n+
Av
~3-4
p-sub
PWR_ON
(a)
RST1
RST2
PWR_ON
RD (
φ
1)
CALIB (
φ
2)
f
CK
=100 MHz
160 ns
LATCH
(b)
Fig. 1. (a) Schematic of the proposed DC-coupled pixel and, (b) related
timing (clocking stimuli) with f
CK
=100 MHz. RD, CALIB and LATCH signals
are used by the column readout circuitry.
A Fast Monolithic Active Pixel Sensor with
Pixel Level Reset Noise Suppression and Binary
Outputs for Charged Particle Detection
Yavuz Değerli, Member, IEEE, Grzegorz Deptuch, Member, IEEE, Nicolas Fourches, Member, IEEE,
Abdelkader Himmi, Yan Li, Pierre Lutz, and Fabienne Orsini
I

The classical 3-T photodiode CMOS active pixels need
some modifications to be used for aggressive readout time
scenarios in future vertex detectors of high energy physics
experiments. The maximum charge-to-voltage conversion
factor (CVF) achievable is limited to 20 µV/e
-
with n-well/p-
epi diodes in mainstream CMOS technologies. This is not
sufficient to overcome the residual pixel-to-pixel and column-
to-column fixed-pattern-noise (FPN). In order to implement
on-line data sparsification some in-pixel amplification of the
signal is required for higher CVF. The amplifier has to be
placed as close as possible to the detection diode for the
optimum noise performance. The correlated sampling
processing (CDS) can be performed on the amplified signal
with less risk of deterioration of the noise performance. The
CDS processing implemented in-pixel is required to suppress
the reset noise and pixel-to-pixel offset non-uniformities. The
latest are typically of the order of the signal generated by an
impinging particle. The first step towards the on-chip data
processing was the MIMOSA6 chip [2]. The design showed
the usefulness of the two memory cells implemented in pixel
for signal extraction taking the difference of the samples
latched in two time intervals. In this previous design residual
pixel-to-pixel FPN was too important to use effectively
discriminators implemented on the chip. Those were tested
separately assessing their good performances.
II. P
IXEL DESIGNS
A. DC-Coupling Pixel Design
The pixel design with DC-coupling of the amplifier to the
charge sensing diode is the basis of the chip design described
in this paper. This pixel architecture, derived from [3] and
proposed in [4], uses a common-source (CS) preamplifying
stage placed closest to the detector, and double sampling
circuitry with a serial capacitor, a switch, and a source follower
(SF) combination to store the reset level of the detector
(Fig. 1a). This reset level is memorized until the next readout
of the pixel during which it is eliminated by subtracting from
the signal. The short interval between readouts in this
application give us the opportunity to store easily the reset
level of the detector in the pixel. Offset mismatches of the
amplifiers are also suppressed as a result of the double
sampling process. The threshold voltage mismatches of the
SFs are successively corrected by a second double sampling
process performed at the column level.
The voltage V
RD
, sampled by the readout circuitry during the
RD phase, is the signal which also comprises the offset of the
SF stage. The voltage V
CALIB
, sampled during CALIB phase, is
the offset of SF stage. The useful signal is the difference
between these two levels, free from the reset noise and offset
mismatches of the CS and SF stages.
This pixel achieves high CVF using only 8 transistors in the
pixel. The amplifier is based on the NMOS transistor common
source architecture with NMOS transistor diode connected
load, both operated in strong inversion. The total voltage gain
is the ratio of the transconductances of the current source
transistor and the load one. The DC current bias of the
amplifier is determined by the voltage across the charge
collecting diode. Further pixel design details can be found in
[4]. SPICE simulations show that the pixel can be read in
100 ns. In the timing shown in Fig. 2b, additional 40 ns for
discrimination and 20 ns to simplify the digital part of the
whole chip were added.
B. Optional AC-Coupling Pixel Design
The pixel design with the direct AC-coupling of the
amplifier to the charge sensing diode was used as a test
structure for the current chip design. The pixel architecture
uses an auto-reverse polarized charge collecting diode [5], in-
pixel amplifier AC-coupled to the charge sensitive element and
circuitry for CDS (Fig. 2a). The CDS circuitry is similar to that
used in the DC-coupled pixel version. The charge sensitive
element is a two diode system, with an n-well/p-epi diode,
collecting the charge available after particle impact, and a p-
plus/n-well diode, providing a constant reverse bias of the first
one.
PWR_ON
Pixel
Vr1
V
DD
Ib
RST2
MOSCAP
SF
Vr2
RD
CALIB
Column
PWR_ON
Av
~15-20
(a)
(b)
Fig. 2. a) Schematic of the proposed AC-coupled pixel, and b) principle of
the direct AC coupling of the auto-reverse polarized charge sensitive element
and the amplifier.

PWR_ON
RST1
RST2
Pixel sub-array 1
(32x32)
Pixel sub-array 2
(32x32)
Pixel sub-array 3
(32x32)
Pixel sub-array 4
(32x32)
binary outputs (4)
………………
analog outputs(8)
RD
CALIB
LATCH
Analog
buffers
Discriminators (24)
Control Logic
MUX
(a)
(b)
(c)
Fig. 3. a) Block diagram, b) layout and c) photography of the realized
prototype chip.
The signal of the charge sensitive element is delivered to the
amplifier via the series capacitance obtained by placing the
polysilicon plate over the n-well area, as it is shown in Fig. 2b.
The gate oxide is used providing a high value of the coupling
capacitance. The signal is then amplified with a voltage gain
about 15-20, aiming at total CVF about 150 µV/e
-
.
The principle of the direct AC coupling of the auto-reverse
polarized charge sensitive element and the amplifier is shown
in Fig. 2b. The choice of AC-coupling instead of DC-coupling
allows independent bias of the input transistor in the amplifier
from the potential settled on the n-well region during the
detector operation. At the same time, the n-well diode is
polarized with the maximum voltage available in the
technology process bearing the optimization of the charge
collection process. Since the second pixel does not use reset
transistor for the diode, the CDS is used to extract the signal in
subtraction from the reference level. The reference level for
each new measurement is the state from the previous readout
cycle.
III. ARCHITECTURE OF THE CHIP
A test chip was designed using a 0.25 µm CMOS digital
process available through MOSIS. The chip consists of four
sub-arrays of 32x32 pixels each, 24 column-level
discriminators for signal sparsification, a fully programmable
digital sequencer and output multiplexers for binary outputs, as
it is shown in Fig. 3. The pixel pitch is 25 µm. The bottom
three arrays contain the DC-coupling pixel type. The three
arrays were designed aiming at different values of CVFs with
different diode sizes. The first array from the top of the chip is
built with the AC-coupling pixel type.
The chip readout is organized in columns processed in
parallel. The first 24 columns are connected to discriminators,
multiplexed onto 4 outputs. The last 8 columns of 32 are not
connected to discriminators. Their analog outputs can be
observed directly on the output pads. These direct outputs were
used for testing of pixels with the results presented in the latter
part of the paper. An additional output of the eights column of
the group of columns with analog outputs allows to examine
internal point of the amplifier before the clamping capacitance
used for CDS processing.
The digital part includes two circuits. One is the digital
control circuit, which is fully programmable and generates the
patterns necessary for addressing, resetting and double
sampling of the signals in pixels in a column parallel way. The
rows are selected sequentially using a multiplexer every 16
clock cycles. The pattern is loaded to the chip serially during a
programming phase at low frequency. The second circuit
realizes a temporal multiplexing of the binary outputs signals
(column discriminators) at a frequency value half that of the
main clock frequency.
The design of comparators is based on an auto-zeroed
amplifying stage and a dynamic latch, as it is shown in Fig. 4.
They are an improved version of the previous design
MIMOSA6 presented in [6][2]. The architecture was modified
to use MOS capacitors instead poly-poly linear capacitors,
because the fabrication process used does not feature this type
of capacitors. To obtain a good linearity, a care had to be taken
MAPS chip

to bias the capacitors in the accumulation regime. Level
shifters before capacitors were used for this purpose. Thanks to
the MOS capacitors, which have small dimensions, the size of
the comparators is the same as the ones used in the previous
design (220 µm x 25 µm).
The discriminators substract V
RD
from V
CALIB
for each pixel,
and compare it with the reference differential voltage
21 VrefVrefVref =
.
C
1
+
_
C
1
+
_
φ2
φ2
S
1
S
2
Vref1
Vref2
Vin
S
3
S
4
φ1
φ1
V
OS1
+
_
φ1
S
5
+
_
φ1
S
6
Latch
V
OS2
V
OS
L
LA
TC
Q
A
1
A
2
Q
LATCH
Fig. 4. Bloc diagram of the offset compensated comparator.
IV. T
EST RESULTS
Two kinds of measurements were performed on the chip.
At the first step, the analog outputs were tested with a digital
oscilloscope. The digital part generates a signal synchronized
with the access to the first row of the pixel array. The analog
signal from a single, selected column was examined using this
synchronizing signal. It was possible to observe the signal of
one single pixel in this way. During the tests with the
oscilloscope, the clock operating frequency was of the order of
10 MHz, allowing clearly observing different phases (the first
readout, reset of the charge collecting diode, reset of the
clamping capacitance, second readout – calibration in the pixel
access). At the latter step, measurements with main clock
frequency of up to 100 MHz were also successfully performed.
A thorough study of the analog outputs was made. The arrays
of pixels with the DC-coupling were tested at the beginning as
the basic option. The tests of the matrix containing pixels with
AC coupling were also started. Experiencing some problems
during the tests of AC-coupling pixels, the results of the DC-
coupling option are presented in this paper only. The tests of
the AC-coupling will be continued.
Fig. 5 shows the direct analog output signal observed.
Note that the 2 levels for each pixel (V
RD
and V
CALIB
). The
black part is the pedestal and the grey lines correspond to the
signal. The useful signal is the difference between these two
levels. Tests without the source showed that the double
sampling could eliminate offset dispersions of the in-pixel
amplifying stage. The offset dispersions of the source follower
output stage are to be corrected later by the column readout
circuitry (discriminators). The two samples were recorded for
each pixel and then subtracted offline, resulting in dispersions
level less than 1 mV. The typical consumption of each pixel is
reduced to 60 µA (the pixel dissipates only when it is powered-
up).
Pixel
(
n
)
Pixel
(
n+1
)
V
RD
V
CALIB
high-amplitude hit
Fig. 5. Output analog signal from 12 pixels of a column recorded on a scope
(50 mV/div.). The useful signal for each pixel is the difference between these
two levels, normally extracted by the column readout circuitry. A high-
amplitude hit is clearly detected on pixel (n) during the read phase,
corresponding to full energy deposition of the X photon. Other hits appear
distinctly.
The ability to detect ionising radiation was tested with soft
X ray photons from a
55
Fe source in a second step. A 9.8 mCi
55
Fe source was placed in the dark box at approximately 1 cm
of the chip with no material in between. After 15 minutes of
the acquisition time, the hits could be seen on the oscilloscope
as jumps on the output signal during the RD phase, as it is
shown in Fig. 5 and 6. The conversion factors for different
pixel architectures were grossly estimated from the maximum
signal observed
1
. A good agreement comparing to ones
simulated was obtained. The conversion between the measured
voltage and the charge collected by the diode was estimated
knowing the energy of the photons from the source to be
5.9 keV for the dominating emission mode, corresponding
roughly to 1600 e
-
. The knowledge of the CVF allows
estimating of noise, which does not exceed 20 e
-
ENC for the
worst case, i.e. the pixel with lowest CVF (@f
CK
=100 MHz
and with a measurement bandwidth of 200 MHz). The results
obtained in this way can be only be considered as preliminary,
allowing however demonstration of good ionising radiation
detection capabilities, with low noise and low pixel-to-pixel
DC level dispersion, of the new pixel architecture. The results
obtained in tests are summarized in Table I.
The signal for an
55
Fe source is higher than the one which
would be expected for a MIP (an average of 80 e
-
/µm x 6 µm =
480 e
-
), so the tests of the MIPs detection will be the next step
forward. The good signal to noise ratio shows MIP detection
should be possible. Beam tests are expected to clarify this
issue.
The binary outputs were all proved functional.
1
The calibration is done, assuming that maximum signal observed for the
exposition time correspond to the events of the photon impacts with
conversion taking place in the n-well volume or in the depletion zone of the
charge collecting diode, where the full quantity of the generated charge is
collected within one pixel.

Citations
More filters
Journal ArticleDOI
TL;DR: In this article, the most recent development of active pixel sensors (MAPS) at IPHC and IRFU addressing this issue is reviewed, combining pixel array, column-level discriminators and zero suppression circuits.
Abstract: CMOS Monolithic Active Pixel Sensors (MAPS) have demonstrated their strong potential for tracking devices, particularly for flavour tagging. They are foreseen to equip several vertex detectors and beam telescopes. Most applications require high read-out speed, which imposes sensors to feature digital output with integrated zero suppression. The most recent development of MAPS at IPHC and IRFU addressing this issue will be reviewed. The design architecture, combining pixel array, column-level discriminators and zero suppression circuits, will be presented. Each pixel features a preamplifier and a correlated double sampling (CDS) micro-circuit reducing the temporal and fixed pattern noises. The sensor is fully programmable and can be monitored. It will equip experimental apparatus starting data taking in 2009/2010.

55 citations


Cites background from "A fast monolithic active pixel sens..."

  • ...The discriminator design has been detailed in [9]....

    [...]

  • ...The timing diagram and more details on the CDS can be found in [9]....

    [...]

  • ...Figure 4(a) shows a standard common source (CS) amplifier [9]....

    [...]

Journal ArticleDOI
TL;DR: In this paper, the performance of the MIMOSA8 (HiMAPS1) chip is reported, which is a 128×32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs.
Abstract: We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

40 citations


Cites background from "A fast monolithic active pixel sens..."

  • ...This scheme proved to be successful up to now and has allowed some good preliminary measurement results [4]....

    [...]

  • ...The new aspects of the pixel have already been described in [4]....

    [...]

  • ...For further details on the architecture of this chip see our previous work [4]....

    [...]

Journal ArticleDOI
TL;DR: In this article, the use of continuous time charge amplification and shaping is proposed for processing the signal delivered by CMOS pixel sensors in charged particle tracking applications, which aims at exploiting the large scale of integration of modern deep submicron CMOS technologies to incorporate into the design of a single device both the potential for thin detector fabrication, inherent in the concept of monolithic active pixel sensors (MAPS), and the data sparsification capabilities featured by hybrid pixels.
Abstract: In this paper, the use of continuous time charge amplification and shaping is proposed for processing the signal delivered by CMOS pixel sensors in charged particle tracking applications. Such a choice aims at exploiting the large scale of integration of modern deep submicron CMOS technologies to incorporate into the design of a single device both the potential for thin detector fabrication, inherent in the concept of monolithic active pixel sensors (MAPS), and the data sparsification capabilities featured by hybrid pixels. With respect to classical MAPS, adoption of the above readout method involves a substantial change in the guidelines for the design of the front-end electronics and of the whole elementary cell, in order not to jeopardize the collection efficiency of the sensitive electrode. For the purpose of supporting the feasibility of the proposed solution, the paper discusses some experimental data and simulation results relevant to monolithic CMOS sensor prototypes, fabricated in a 0.13 mum technology, which were designed according to the mentioned rules. Finally, the performances of an all NMOSFET charge preamplifier, suitable for improving charge collection efficiency, are investigated through circuit simulations

24 citations

Journal ArticleDOI
TL;DR: The HiMAPS2 (HiMAPS16) as discussed by the authors is the basis of the final sensor of the EUDET-JRA1 beam telescope which will be installed at DESY in 2009.
Abstract: Recently, CMOS Monolithic Active Pixels Sensors (MAPS) have become strong candidates for pixel detectors used in high energy physics experiments. A very good spatial resolution lower than 5 mum can be obtained with these detectors. A recent fast MAPS chip, designed in AMS CMOS 0.35 mum Opto process and called MIMOSA16 (HiMAPS2), was submitted to foundry in June 2006. The chip is a 128times32 pixels array where 8 columns have analog test outputs and 24 columns have their outputs connected to offset compensated discriminator stages. The pixel array is addressed row-wise. The array is divided in four blocks of pixels with different charge-to-voltage conversion factors and is controlled by a serially programmable sequencer. The sequencer operates as a pattern generator which delivers control signals both to the pixels and to the column-level discriminators. Discriminators have a common adjustable threshold. This chip is the basis of the final sensor of the EUDET-JRA1 beam telescope which will be installed at DESY in 2009. In this paper, laboratory tests results using a 55Fe source together with beam tests results obtained at CERN using Minimum Ionizing Particles (MIPs) are presented.

19 citations


Cites background or methods from "A fast monolithic active pixel sens..."

  • ...ination designed for charged particle detection, the MIMOSA8 (HiMAPS1) chip, has exhibited very encouraging performances [2], [3]....

    [...]

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    [...]

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    [...]

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    [...]

Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this paper, the performance of the MIMOSA8 chip is reported, which is a representative of the CMOS sensors development option considered as a promising candidate for the vertex detector of the future International Linear Collider (ILC).
Abstract: We report on the performance of the MIMOSA8 chip. The chip is a 128/spl times/32 pixels array where 8 columns have analog direct outputs and 24 have discriminated outputs. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the vertex detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the 8 analog outputs. Analog data, without and with a /sup 55/Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clocking frequency is increased even up to 150 MHz (13.6 /spl mu/s readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency.

15 citations


Cites background from "A fast monolithic active pixel sens..."

  • ...This scheme proved to be successful up to now and has allowed some good preliminary measurement results [4]....

    [...]

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    [...]

  • ...For further details on the architecture of this chip see our previous work [4]....

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References
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Journal ArticleDOI
15 Oct 2000
TL;DR: In this paper, a monolithic active pixel sensor (MAPS) for charged particle tracking based on a novel detector structure was proposed, simulated, fabricated and tested, which is inseparable from the readout electronics, since both of them are integrated onto the same, standard for a CMOS process.
Abstract: A monolithic active pixel sensor (MAPS) for charged particle tracking based on a novel detector structure was proposed, simulated, fabricated and tested. The detector designed accordingly to this idea is inseparable from the readout electronics, since both of them are integrated onto the same, standard for a CMOS process, low-resistivity silicon wafer. The individual pixel is comprised of only 3 MOS transistors and a photodiode collecting the charge created in a thin undepleted epitaxial layer. This approach provides the whole detector surface sensitive to radiation (100% fill factor) with reduced pixel pitch(very high spatial resolution). This yields a low cost, high resolution and thin detecting device. The detailed device simulations using an ISE-TCAD package have been carried out in order to study a charge collection mechanism and to validate the proposed idea. Consequently, two prototype chips have been fabricated using 0.6 /spl mu/m and 0.35 /spl mu/m CMOS processes. Special radiation tolerant layout techniques were used in the second chip design. Both chips were tested and fully characterised. The pixel conversion gain was calibrated using 5.9 keV photons and prototype devices were exposed to the 120 GeV/c pion beams at CERN. Obtained results preceded by general design ideas and simulation results are reviewed.

123 citations

Journal ArticleDOI
TL;DR: In this article, a column-based, low power, fully offset compensated multistage comparator (discriminator) was developed to read out the active pixels in a monolithic active pixel sensors (MAPS) based detector.
Abstract: Future high energy physics experiments will require the development of a linear collider in the TeV region such as TESLA. Because of physics requirements it will be necessary to make precision vertex measurements. This makes a high-resolution vertex detector an essential part of the detecting system. One of the possibilities is to develop a CMOS monolithic active pixel sensors (MAPS) based detector. A planned prototype chip for the TESLA developments would include an array of identical pixels with their addressing circuits, signal processing within the chip, data sparsification, and analogue to digital conversion. For this purpose we have developed a column-based, low power, fully offset compensated multistage comparator (discriminator) to read out the active pixels. For one of the versions implemented, a resolution better than 1 mV was obtained at operating speeds higher than 10 MHz. The power dissipation is of the order of 200 /spl mu/W. A test chip was designed on a 0.35 /spl mu/m CMOS process from AMI Semiconductor. As the pixel pitch is only 28 /spl mu/m, the dimensions of the comparator are 300 /spl mu/m/spl times/28 /spl mu/m. This design is compatible with the clocking scheme of the pixel array.

39 citations


"A fast monolithic active pixel sens..." refers methods in this paper

  • ...They are an improved version of the previous design MIMOSA6 presented in [6][2]....

    [...]

Journal ArticleDOI
01 Jan 2003
TL;DR: In this article, a 30 /spl times/128 pixel prototype chip is presented, featuring fast, column parallel signal processing. But the pixel output is a differential current signal proportional to the difference between the charges collected in two consecutive time slots, and the readout of the pixel is two-phase matching signal discrimination circuitry implemented at the end of each column.
Abstract: Monolithic Active Pixel Sensors constitute a viable alternative to Hybrid Pixel Sensors and Charge Coupled Devices for the next generation of vertex detectors. Possible application will strongly depend on a successful implementation of on-chip hit recognition and sparsification schemes. These are not a trivial task, first because of very small signal amplitudes (/spl sim/mV), originated from charge collection, which are of the same order as natural dispersions in a CMOS process, secondly because of the limitation to use only one type of transistor over the sensitive area. The paper presents a 30 /spl times/ 128 pixel prototype chip, featuring fast, column parallel signal processing. The pixel concept combines on-pixel amplification with double sampling operation. The pixel output is a differential current signal proportional to the difference between the charges collected in two consecutive time slots. The readout of the pixel is two-phase, matching signal discrimination circuitry implemented at the end of each column. The design of low-noise discriminators includes automatic compensation of offsets for individual pixels. The details of the chip design are presented. Difficulties, encountered from being the first attempt to address on-line hit recognition, are reported. Performances of the pixel and discriminator blocks, determined in separate measurements, are discussed. The essential part of the paper consists of results of first tests performed with soft X-rays from a /sup 55/Fe source.

22 citations

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Q1. What are the contributions in "A fast monolithic active pixel sensor with pixel level reset noise suppression and binary outputs for charged particle detection" ?

In order to develop precision vertex detectors for the future linear collider, fast active monolithic active pixel sensors are studied.