A fast-settling PLL frequency synthesizer with direct frequency presetting
18 Sep 2006-pp 741-750
TL;DR: A PLL frequency synthesizer with frequency presetting is implemented in a 0.35mum CMOS process and can automatically compensate for frequency variation with temperature.
Abstract: A PLL frequency synthesizer with frequency presetting is implemented in a 0.35mum CMOS process and occupies 0.4mm2. The output frequency is between 560 and 820MHz, the supply is 3.3V, the measured settling time is <10mus and the phase noise is -85dBe/Hz at 10kHz offset. The synthesizer can automatically compensate for frequency variation with temperature
Citations
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TL;DR: In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process, and the detected phase error is coarsely compensated by dynamically changing the divide ratio of the frequency divider.
Abstract: This paper presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratio of the frequency divider. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process, thereby reducing the settling time. To further enhance the locking speed, an auxiliary charge pump is employed to supply currents to the loop filter during the fast-locking mode to facilitate a rapid frequency acquisition. The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is considerably improved over previous bandwidth-switching method. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.3 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc.
86 citations
Cites background or methods from "A fast-settling PLL frequency synth..."
...Consequently, this approach often requires complex calibrations to realize such a lookup table [7]....
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...To address this tradeoff between settling time and loop bandwidth, several works were introduced [1], [2], [7]–[14]....
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...One design approach is to utilize a pre-determined lookup table to adjust the output frequency immediately [7], [8]....
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TL;DR: A VCO frequency calibration technique suitable for a wideband fractional-N PLL that achieves a single-bit calibration time of only kTREF for obtaining a frequency resolution of fREF/k, and compared to the conventional techniques, which is the best performance in terms of the calibration time versus resolution.
Abstract: A VCO frequency calibration technique suitable for a wideband fractional-N PLL is presented. It provides a fast and high-precision search for an optimal discrete tuning curve of an LC VCO during the coarse tuning process in a fractional-N PLL. A high-speed frequency error detector (FED) converts the VCO frequency to a digital value and computes the exact frequency difference from a target frequency. A minimum error code finder finds an optimal code that is closest to the target frequency. Due to the pure digital domain operation, a ΔΣ modulator in PLL can be deactivated during the calibration process, which makes this technique fast and accurate especially for a ΔΣ fractional-N PLL. We achieve a single-bit calibration time of only kTREF for obtaining a frequency resolution of fREF/k, and compared to the conventional techniques, which is the best performance in terms of the calibration time versus resolution. Such fast VCO frequency calibration can greatly reduce the total lock time in a PLL. A 2.3-3.9 GHz fractional-N PLL employing the proposed calibration technique is implemented in 0.13 μm CMOS. Successful operation is verified through experimental results. The measured calibration time for a 6-bit capbank is 1.09 and 2.03 μs for a frequency resolution of 19.2 and 4.8 MHz, respectively.
67 citations
TL;DR: In this article, the authors proposed two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metaloxide-semiconductor (MOS) transistor.
Abstract: This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits
32 citations
Cites background or methods from "A fast-settling PLL frequency synth..."
...Compared with conventional MOS VCOs, power dissipations of the hybrid VCO circuits are very low, although the size of the MOS transistors is not very small....
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...VCO circuits, and various circuit techniques have been developed to compensate the temperature effect [29]....
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...Compared to conventional MOS VCOs, the power dissipations of the hybrid VCOs is very low....
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...12(a) and (b) shows the dependence of the drift of the center frequencies of both VCOs on operating temperature with temperature compensated current source....
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...Although the oscillation frequencies of the hybrid VCOs are shifted by parameter dispersion, we can use the well-established compensation techniques in the design of conventional VCOs [29] to counteract the effect....
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TL;DR: A novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors is proposed and a technique to compensate parameter dispersions of SEDs is proposed.
Abstract: This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.
23 citations
Cites background from "A fast-settling PLL frequency synth..."
...We have demonstrated that parameter dispersions in the hybrid VCO circuit can be well compensated by adjusting [4], [20]....
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TL;DR: A wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique that shows good robustness over environmental variation and can avoid the risk that SILPLL may lock to the wrong frequency or even fail to lock is proposed.
Abstract: This paper proposes a wideband subharmonically injection-locked PLL (SILPLL) with adaptive injection timing alignment technique. The SILPLL includes three main circuit blocks: one-oscillator-period constant-delay (OOPCD) divider, timing-adjusted phase detector (TPD), and pulse generator (PG). The proposed injection timing alignment technique can align the injection timing adaptively in a wide range of the output clock frequency using the two blocks (OOPCD and TPD) and a falling edge locking scheme of pulses. It can avoid the risk that SILPLL may lock to the wrong frequency or even fail to lock. The PG block is used for half-integral injection to relax the tradeoff between the phase noise of SILPLL and the output frequency resolution. The OOPCD circuit occupies a negligible area. After the injection timing alignment is finished, the OOPCD is powered off so that no extra power is consumed. The SILPLL is implemented in the 65-nm 1P9M CMOS process. It consumes 8.6 mW at 1.2 V supply and occupies an active core area of $1 \times 0.6$ mm2. The measured output frequency range is 2.4~3.6 GHz with an output frequency resolution of 200 MHz and the phase noise is −127.6 dBc/Hz at an offset of 1 MHz from a carrier frequency of 3.4 GHz. The rms jitter integrated from 1 kHz to 30 MHz is less than 112 fs for all the covered frequency points. Under the supply voltage range from 1.1 to 1.3 V and the temperature range from −20 °C to 70 °C, the rms jitter variation of all the covered frequency points is less than 27 fs, which shows good robustness over environmental variation.
23 citations
Cites background from "A fast-settling PLL frequency synth..."
...The integer-N PLLs are widely used for clock generation due to its simplicity [5]–[10]....
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References
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TL;DR: In this article, a delta-sigma (Delta-Sigma) modulation and fractional-N frequency division technique for indirect digital frequency synthesis using a phase-locked loop (PLL) is described.
Abstract: A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >
604 citations
"A fast-settling PLL frequency synth..." refers background in this paper
...Recently fractional-N PLL frequency synthesizers were proposed [3][4], but they produce additional fractional spurs that are hard to remove....
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IBM1
TL;DR: A salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount that achieves fast locking and minimizes output jitters.
Abstract: This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range.
253 citations
"A fast-settling PLL frequency synth..." refers background in this paper
...In order to realize a fast-settling PLL frequency synthesizer, dynamic loop-bandwidth control has been proposed [1][2]....
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TL;DR: In this article, a phase-locked loop with a fast-locked discriminator-aided phase detector (DAPD) is presented, which reduces the phase pull-in time and enhances the switching speed, while maintaining better noise bandwidth.
Abstract: A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-/spl mu/m CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW.
152 citations
"A fast-settling PLL frequency synth..." refers background in this paper
...In order to realize a fast-settling PLL frequency synthesizer, dynamic loop-bandwidth control has been proposed [1][2]....
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TL;DR: Low-power and low-area algorithmic techniques are used in the modified sigma-delta modulator in order to make it a feasible option and it is shown that the resulting modulator meets the GSM specifications and has a total power consumption of 2 mW at 1-GHz operation.
Abstract: A wideband phase-locked-loop (PLL) modulator for wireless applications is reported. This modulator is based on PLL fractional-N frequency synthesis techniques along with sigma-delta modulation to randomize fractional-N spurs. A modified sigma-delta function allows for suppression of sigma-delta noise at lower frequencies, and hence allows for wider loop bandwidth. Also, sigma-delta quantization noise is reduced by using fractional division ratios. Low-power and low-area algorithmic techniques are used in the modified sigma-delta modulator in order to make it a feasible option. It is shown that the resulting modulator meets the GSM specifications and has a total power consumption of 2 mW at 1-GHz operation.
33 citations