Boise State University
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Electrical and Computer Engineering Faculty
Publications and Presentations
Department of Electrical and Computer
Engineering
1-1-2007
A Five-Level )ree-Phase Hybrid Cascade
Multilevel Inverter Using a Single DC Source for a
PM Synchronous Motor Drive
John N. Chiasson
Boise State University
Burak Ozpineci
Oak Ridge National Laboratory
Leon M. Tolbert
University of Tennessee, Knoxville
+is document was originally published by IEEE in Annual IEEE Applied Power Electronics Conference, APEC 2007. Copyright restrictions may apply.
DOI: 10.1109/APEX.2007.357716
A Five-Lev el T hree-Phase Hybrid Cascade
Multilevel Inverter Using a Single DC Source
for a PM Synchronous Motor Drive
John N. Chiasson
1
, Burak Özpineci
2
, and Leon M. Tolbert
2,3
1
ECE Department, MS 2075, Boise State Univ ersity, Boise Idaho 83725, johnchiasson@boisestate.edu
2
Oak Ridge National L aboratory, Oak Ridge TN, ozpinecib@ornl.gov, tolbertlm@ornl.gov
3
ECE Department, University of Tennessee, Knoxville, TN 37996, tolbert@utk.edu.
Abstract— The interest here is in using a single DC power
source to construct a 3-phase 5-level cascade multilevel in verter
to be used as a drive for a PM traction motor. The 5-level inverter
consists of a standard 3-leg inverter (one leg f or each phase) and
an H-bridge in series with each inverter leg, which use a capacitor
as a DC source. It is shown that one can simultaneously maintain
the regulation of the capacitor voltage while achieving an output
voltage wavef orm which is 25% higher than that obtained using
a standard 3-leg inverter by itself.
Index Terms— Multilevel Con verter, PM motor drive
I. INTRODUCTION
A cascade multilevel inverter is a power electronic device
built to synthesize a desired AC voltage from several levels
of DC voltages. Such inverters ha ve been the subject of
research in the last se veral years [1][2][3][4][5], where the
DC levels were considered to be identical in that all of them
were capacitors, batteries, solar cells, etc. In [6], a multilevel
converter was presented in which the two separate DC sources
were the secondaries of two transformers coupled to the utility
AC power. Corzine et al [7] have proposed using a single
DC power source and capacitors for the other DC sources. A
method was given to transfer power from the DC power source
to the capacitor in order to regulate the capacitor voltage. A
similar approach was later (but independently) proposed by
Du et al [8]. These approaches required a DC power source
for each phase. The approach here is very similar to that of the
Corzine et al [7] and Du et al [8] with the important exception
that a standard 3-leg inverter is used for the first power source
(one leg for each phase) so that a single DC power source is all
that is required for three phase. This topology was proposed
by one of the authors in [9].
Specifically, the interest here is in using a single DC power
source connected to a standard 3-leg inverter which in turn
is connected to capacitors to form a 3-phase 5-level cascade
multilevel inverter to be used as a dri ve for a PM traction
0
Prepared by the Oak Ridge National Laboratory, Oak Ridge, Tennessee
37831, managed by UT-Battelle for the U.S. Department of Energy under
contract DE-AC05-00OR22725.
The submitted manuscript has been authored by a contractor of the U.S.
Government under Contract No. DE-AC05-00OR22725. Accordingly, the U.S.
Gov e rnment retains a non-exclusive, royalty-free license to publish from the
contribution, or allow others to do so, for U.S. Government purposes.
motor. The 5-level inverter consists of a standard 3-leg inverter
(one leg for each phase) and an H-bridge in series with each
inverter leg, which uses a capacitor as a DC source. It is show n
that one can simultaneously maintain the regulation of the
capacitor voltage while achieving an output voltage wa veform
which is 25% higher than that obtained using a standard 3-leg
inverter by itself.
II. M
ULTILEVEL INVERTER ARCHITECTURE
Fig. 1 shows a DC source connected to a single le g of a
standard 3-leg inverter.
dc
V
1
S
2
S
3
S
4
S
5
S
6
S
1
v
2
v
DC
Source
+
-
C
2
dc
V
+
-
+
-
+
-
v
c
i
i
Fig. 1. One leg of a 3-leg inverter connected to a full H-bridge with a
capacitor DC source.
The output voltage v
1
of this leg (with respect to the ground)
is either +V
dc
/2 (S
5
closed) or −V
dc
/2 (S
6
closed). This
leg is connected in series with a full H-bridge which in turn
is supplied by a capacitor voltage. If the capacitor is kept
charged to V
dc
/2, then the output voltage of the H-bridge can
take on the values +V
dc
/2 (S
1
&S
4
closed), 0 (S
1
&S
2
closed
or S
3
&S
4
closed), or −V
dc
/2 (S
2
&S
3
closed). An example
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output wave form that this topology can achieve is shown in the
top of Fig. 2. When the output voltage v = v
1
+ v
2
is required
to be zero, one can either set v
1
=+V
dc
/2 and v
2
= −V
dc
/2
or v
1
=+V
dc
/2 and v
2
=+V
dc
/2.Itisthisflexibility in
choosing how to make that output voltage zero that is exploited
to regulate the capacitor voltage. In more detail, consider 2.
π
2
2/
dc
V
21
vvv +=
i
π
π
1
θ
1
θ
1
θ
1
θ
π
2
π
π
π
2
2/
dc
V
2/
dc
V
−
2/
dc
V
−
2/
dc
V
2/
dc
V
2/
dc
V
−
2/
dc
V
−
2/
dc
V
2/
dc
V−
dc
V
dc
V−
1
θ
π
π
2
π
2
2
v
1
v
1
v
2
v
Fig. 2. To make the output voltage zero for θ
1
≤ θ ≤ π, one can either
set v
1
=+V
dc
/2 and v
2
= −V
dc
/2 (bottom left) or v
1
=+V
dc
/2 and
v
2
=+V
dc
/2 (bottom right).
During θ
1
≤ θ ≤ π, the output voltage in Fig. 2 is zero and
the current i>0.IfS
1
&S
4
are closed (so that v
2
=+V
dc
/2)
along with S
6
closed (so that v
1
= −V
dc
/2), then the capacitor
is discharging (i
c
= −i<0 see Fig. 1) and v = v
1
+ v
2
=0.
On the other hand, if S
2
&S
3
are closed (so that v
2
= −V
dc
/2)
and S
5
is also closed (so that v
1
=+V
dc
/2), then the capacitor
is charging (i
c
= i>0 see Fig. 1) and v = v
1
+ v
2
=0.
The case i<0 is accomplished by simply reversing the
switch positions of the i>0 case for charge and discharge of
the capacitor. Consequently, the method consists of monitoring
the output current and the capacitor voltage so that during
periods of zero voltage output, either the switches S
1
,S
4
, and
S
6
are closed or the switches S
2
,S
3
,S
5
are closed depending
on whether it is necessary to charge or discharge the capacitor.
Remark
As Fig. 2 illustrates, this method of regulating the capacitor
voltage depends on the voltage and current not being in phase.
That is, one needs positiv e (or negative) current when the
voltage is passing through zero in order to charge or discharge
the capacitor. Consequently, the amount of capacitor voltage
the scheme can regulate depends on the power factor.
III. S
IMULATION RESULTS USING MULTILEVEL PWM
A simulation of the multilevel conve rter dri v ing a PM
synchronous machine was carried out. The motor is controlled
using a standard field-oriented controller [10]. The blocks
marked phase 1, phase 2, and phase 3 contain the modeling
of the multilevel converter. The switching scheme is based
on the standard multilevel PWM scheme [11]. The scheme is
modified so that during those time periods when the converter
is supplying zero volts, either the switches S
1
,S
4
, and S
6
are
closed or the switches S
2
,S
3
,S
5
are closed depending on
whether the current is positive or negative and whether it is
necessary to charge or discharge the capacitor.
The DC link voltage V
dc
was set to 200 V so that the 3-
leg inverter puts out ±100 V. The capacitors were regulated
to 100 V. The motor’s inertia is J =0.1 kg-m
2
,themotor
has n
p
=4pole-pairs, the stator resistance is R
S
=0.065
Ohms, the stator inductance is L
S
=3mH, the torque/back-
emf constant K
T
= K
b
=0.37 Nm/A (V/rad/sec) and the
load torque τ
L
=19Nm. The capacitor value is C =0.01 F.
For comparison purposes, simulations were performed using
both the multilevel inverter of Fig. 1 capable of supplying
±200 V and a standard 3-leg inverter (i.e., only the bottom
half of Fig. 1) capable of supplying ±100 V. Though the
multilevel inverter can provide up to ±200 V, it cannot do this
and maintain regulation of the capacitor voltages. As pointed
out in the above remark, the ability to regulate the capacitor
voltage depends on the power factor of the load. The PM
motor was run to achieve the highest possible speed under the
given load and available voltage. This is shown in Figs. 3 and
4. The standard 3-leg inverter could only achieve a maximum
speed of 212 rad/sec while the proposed multilevel inverter
could drive the motor up to 275 rad/sec using the same DC
source voltage.
0 1 2 3 4 5 6
-50
0
50
100
150
200
250
300
Rotor Speed (Max = 212 rad/sec)
Seconds
Radians/Second
Fig. 3. Rotor speed achievable using a standard 3-leg inverter
0 1 2 3 4 5 6
-50
0
50
100
150
200
250
300
Rotor Speed (Max = 275 rad/sec)
Seconds
Radians/Second
Fig. 4. Rotor speed achievable using the proposed multilevel inverter.
The corresponding voltages for the speed trajectories of Fig.
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3andFig.4areshowninFig.5andFig.6,respectively.The
standard 3-leg inverter produces a nearly six step waveform
of V
dc
/2 = 100 V maximum corresponding to a fundamental
voltage of
4V
dc
2π
= 127 V peak while the multilevel inverter is
supplying 170 V peak in steady state and up to 180 V before
steady state.
0 2 4 6
-200
-100
0
100
200
Stator Voltage Phase 1
Seconds
Volts
Fig. 5. Voltage using a standard 3-leg inverter.
0 2 4 6
-200
-100
0
100
200
Stator Voltage Phase 1
Seconds
Volts
Fig. 6. Voltage obtained using the proposed multilevel inverter.
The corresponding torques for the above trajectories are
showninFig.7andFig.8,respectively.Thepeaktorque
is larger for the cascade mulitilevel inv erter drive because the
motor is being accelerated to a higher speed. The chattering
shown in the torque response of the standard 3-leg in verter is
due to the fact that the voltage is undergoing saturation (see
Fig. 5).
0 1 2 3 4 5 6
0
5
10
15
20
25
30
Motor Torque
Seconds
Newton-meters
Fig. 7. Torque using standard 3-leg inverter.
0 1 2 3 4 5 6
0
5
10
15
20
25
30
Motor Torque
Seconds
Newton-meters
Fig. 8. Torque using proposed multilevel inverter.
The capacitor voltage as a function of time is plotted in Fig.
9 showing that it is kept within about 2 volts of the desired
value. An enlarged view of the capacitor voltage is shown in
Fig. 10 showing the regulation of the voltage in more detail.
The variation in the voltage will be less if one uses a larger
value of capacitance (C =0.01 F here).
0 2 4 6
97.5
98
98.5
99
99.5
100
100.5
Capacitor Voltage
Seconds
Volts
Fig. 9. Capacitor voltage versus time.
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3.48 3.485 3.49 3.495 3.5 3.505 3.51
98
98.5
99
99.5
100
Capacitor Voltage
Seconds
Volts
Fig. 10. Expanded view of the capacitor voltage as a function of time.
IV. C APACITOR VOLTAGE REGUL ATI ON
To illustrate how the capacitor voltage regulation works,
scaled versions of the capacitor voltage, stator voltage, and
stator current for phase 1 are shown in Fig. 11 for a funda-
mental frequency switching scheme (The technique is easier
to illustrate using a fundamental switching scheme though
the PWM scheme uses the same method). Note that the
capacitor discharges when the inverter is supplying ±200 V,
stays constant when the inverter is supplying ±100 V, a nd
recharges when the inverter is supplying 0 V.
5.575 5.58 5.585
-200
-100
0
100
200
Fig. 11. Scaled capacitor voltage, stator current and stator voltage versus
time in seconds.
For example, a little after t =5.575 seconds, the current (in
black) becomes positive and the inverter is supplying 200 V
(blue). The capacitor voltage (red) then decreases. Following
this, when the inverter is only supplying 100 V, the capacitor
voltage is constant. Next, the inverter is producing 0 V and
during this time the capacitor is charged to increase its voltage.
V. D
ISCUSSION AND FUTURE WORK
A five-le vel cascade multilevel inverter topology has been
proposed that requires only a single standard 3-leg inverter and
capacitors as the power sources. The capacitors obtain their
power from the 3-leg inverter allowing the cascade multilevel
inverter to provide significantly more voltage from a given
DC power source than just a three leg inverter alone. It
was shown that the capacitor voltages could be maintained
(regulated) subject to large enough power factor. Both PWM
and fundamental frequency switching schemes can be used.
R
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