A Flexible LDPC/Turbo Decoder Architecture
Summary (2 min read)
- Practical wireless communication channels are inherently “noisy” due to the impairments caused by channel distortions and multipath effect.
- They can both be represented as codes on graphs which define the constraints satisfied by codewords.
- Third, the authors propose a flexible SISO decoder hardware architecture based on the FFU.
- Section 2 reviews the super-code based decoding algorithm for LDPC codes.
2 Review of Super-code Based Decoding Algorithm for LDPC Codes
- Naturally, Turbo decoding procedure can be partitioned into two phases where each phase corresponds to one super-code processing.
- Similarly, LDPC codes can also be partitioned into super-codes for efficient processing as previously mentioned in Section 1.
- Before proceeding with a discussion of the proposed flexible decoder architecture, it is desirable to review the super-code based LDPC decoding scheme in this section.
3 Flexible SISO Module
- The authors propose a flexible soft-input softoutput (SISO) module, named Flex-SISO module, to decode LDPC and Turbo codes.
- To reduce complexity, the MAP algorithm is usually calculated in the log domain .
- For LDPC codes, a Flex-SISO module was used to decode a super-code.
- The soft input values λi(u) are the outputs from the previous Flex-SISO module, or other previous modules if necessary.
- First, the authors decompose a QC-LDPC code into multiple supercodes, where each layer of the parity check matrix defines a super-code.
3.3.1 Review of the Traditional Turbo Decoder Structure
- The traditional Turbo decoding procedure with two SISO decoders is shown in Fig. 7.
- The definitions of the symbols in the figure are as follows.
- The channel LLR values for uk and p(i)k are denoted as λc(uk) and λc(p (i) k ), respectively.
- In the first half iteration, SISO decoder 1 computes the extrinsic value λ1e(uk) and pass it to SISO decoder 2.
- The computation is repeated in each iteration.
3.3.2 Modif ied Turbo Decoder Structure Using Flex-SISO Modules
- In order to use the proposed Flex-SISO module for Turbo decoding, the authors modify the traditional Turbo decoder structure.
- Then it removes the old extrinsic value λ1e(uk; old) from the soft input LLR λ1i (uk) to form a temporary message λ1t (uk) as follows (for brevity, the authors drop the superscript “1" in the following equations) λt(uk) = λi(uk) − λe(uk; old).
- The computation is repeated in each half-iteration until the iteration converges.
- Figure 9 shows an iterative Turbo decoder architecture based on the Flex-SISO module.
- The memory organizations are similar, but with a variety of sizes depending on the codeword length.
4 Design of a Flexible Functional Unit
- The MAP processor is the main processing unit in both LDPC and Turbo decoders as depicted in Fig. 6 and Fig. 9. (25) Figure 13 shows a MAP processor structure to decode the single parity check code.
- Thus, the same look-up table configuration can be applied to the Turbo ACSA unit.
- To support both LDPC and Turbo codes with minimum hardware overhead, the authors propose a flexible functional unit (FFU) which is depicted in Fig. 15.
5 Design of A Flexible SISO Decoder
- Built on top of the FFU arithmetic unit, the authors introduce a flexible SISO decoder architecture to handle LDPC and Turbo codes.
- The boundary β metrics are initialized from an NII buffer (not shown in Fig. 19).
- The decoder first computes λt(u) based on Eq. 5. Prior to decoding, the α and β metrics are initialized to the maximum value.
- While the β unit and the extrinsic-1 unit are working on the first data stream, the α unit can work on the second stream which leads to a pipelined implementation.
- In a parallel processing environment, multiple SISO decoders can be used to increase the throughput.
6 Parallel Decoder Architecture Using Multiple Flex-SISO Decoder Cores
- For high throughput applications, it is necessary to use multiple SISO decoders working in parallel to increase the decoding speed.
- For parallel Turbo decoding, multiple SISO decoders can be employed by dividing a codeword block into several sub-blocks and then each sub-block is processed separately by a dedicated SISO decoder [7, 20, 30, 41, 42].
- APP memory is used to store the initial and updated LLR values.
- Turbo parity memory is used to store the channel LLR values for each parity bit in a Turbo codeword.
- As a case study, the authors have designed a high-throughput, flexible LDPC/Turbo decoder to support the following three codes: 1) 802.16e WiMAX LDPC code, 2) 802.11n WLAN LDPC code, and 3) 3GPP-LTE Turbo code.
- The authors present a flexible decoder architecture to support LDPC and Turbo codes.
- To increase decoding throughput, the authors propose a parallel LDPC/Turbo decoder using multiple Flex-SISO cores.
- The proposed architecture can significantly reduce the cost of a multi-mode receiver.
Did you find this useful? Give us your feedback
Cites background or methods from "A Flexible LDPC/Turbo Decoder Archi..."
...Flexible decoders available in the literature –, , , , , though supporting a wide range of codes, do not address the reconfiguration issue....
...Sun and Cavallaro describe in  a decoder working with 3GPP-LTE turbo codes and WiMAX and WiFi LDPC codes....
Cites background from "A Flexible LDPC/Turbo Decoder Archi..."
...While Sun and Cavallardo  have designed single architecture to process both LDPC and turbo codes by proposing a unified algorithm....
...Multi-mode reconfigurable architectures in  and  have the flexibility to switch between LDPC and turbo decoding-process....
Cites methods from "A Flexible LDPC/Turbo Decoder Archi..."
...A high throughput of 257Mbps is achieved for LDPC mode while a limited throughput of 37.2Mbps in DBTC and 18.6Mbps in SBTC modes are achieved at 400MHz....
Cites methods from "A Flexible LDPC/Turbo Decoder Archi..."
...The architecture for WiMAX/WiFi LDPC codes and 3GPP-LTE turbo code presented in  runs at 500 MHz and achieves the highest throughput among compared architectures with the same complexity as our architecture....
"A Flexible LDPC/Turbo Decoder Archi..." refers methods in this paper
...As a candidate for 4G coding scheme, LDPC codes, which were introduced by Gallager in 1963 [ 13 ], have recently received significant attention in coding theory and have been adopted by some advanced wireless systems such as IEEE 802.16e WiMAX system and IEEE 802.11n WLAN system....