# A gate-level leakage power reduction method for ultra-low-power CMOS circuits

## Summary (2 min read)

### 1. Introduction

- As VLSI devices have grown in complexity and density, their power consumption has become a major design concern.
- High power consumption also impacts battery-powered portable devices by requiring either large battery packs or unacceptably short operating time.
- Methods by Horiguchi, et al., [3] and Mutoh, et al., [4] use circuit and process level changes to reduce the leakage power.
- The authors design methodology is given in section 2. Section 3 describes the gate library characterization process.

### 2. Design Methodology

- This is based on the observation that individual CMOS gates show a variation in the leakage power based on the input vector, as seen in Table 1.
- Modern low-power designs make extensive use of clock-gating.
- Thus, whenever a circuit is put in standby, the latches or flip-flops inside it maintain the last state they were in.
- This has to be done only once, during the logic design phase.
- The authors have done this by building look-up table models as in Table 1 for several kinds of logic gates and then running a simple steady state logic simulation in order to determine the leakage for a given circuit input vector.

### 3. Gate Library Characterization

- In order to efficiently estimate the leakage of a large combinational circuit for a given input pattern, the authors need to develop models for logic gates that give the leakage current drawn by the gate for each of its input patterns.
- Using a circuit-level simulator, such as SPICE, and an appropriate MOSFET device model, the authors determine the leakage current for each input pattern and log the results into a look-up table.
- As an example, Table 1 shows the look-up table for a 2-input NAND gate.
- The values in this table are based on data which was obtained from a major semiconductor manufacturer, which the authors will refer to as “company A,” and is derived from a 0.5 µm CMOS process.

### 4. Input Vector Determination Technique

- Consider a combinational circuit whose input nodes are state bits of an overall sequential circuit which will be put in standby mode.
- The “search problem” for the vector that gives the least leakage power is a very difficult one because of the potentially huge size of the search space.
- In the following, the authors will derive a simple result (9) which gives the number n of vectors required, a priori, for a given desired “quality” of the solution.
- Consider the set of all possible input vectors to the circuit, and consider an experiment by which a vector is chosen at random, with all vectors having the same probability of being chosen.
- Let f(x) and F (x) be the probability density function (pdf) and the cumulative density function (cdf) of X, respectively.

### 5. Latch Designs

- The circuitry used to force the low-power input vector onto the combinational logic should add as little speed and area overhead as possible to the design.
- Solutions such as pass-gate multiplexers and CMOS NAND and NOR gates can be used to force the outputs to the desired value during sleep mode.
- Fig. 2 shows standard static “jamb” latches [6] modified to force a value at the output during sleep mode.
- Fig. 3 shows modified dynamic C2MOS flip-flops [7].
- Clearly, other types of latches and flip-flops can also be modified in similar ways to force appropriate values during sleep mode.

### 6. Experimental Results

- The authors have tested this design methodology on the ISCAS-89 benchmark circuits.
- Table 2 shows the savings realized by this method using the probabilistic technique developed in Section 4 for error tolerances of 5% and 1% and also using a fixed, large sampling of 100,000 input vectors.
- These “savings” represent the percentage difference between the lowest leakage power obtained in each case and the largest leakage found for each circuit during the 100,000 vector run, relative to this largest leakage.
- Thus, one may think of these as being potential, or best case, savings.

### 7. Conclusion

- The authors have proposed a novel design method that can be used during logic design to reduce the leakage power of CMOS circuits that use clockgating to reduce the dynamic power dissipation.
- Using minimal additional circuitry, the authors modify the original logic design to force the combinational logic into a low-leakage state during an idle period.
- To find such a low-leakage state, the authors have developed an efficient algorithm that determines a good input vector using a sampling of random vectors.
- The size of this sampling is determined a priori using user-supplied quality measures.
- The authors have demonstrated this method on the ISCAS-89 benchmark circuits and shown leakage power reductions of up to 54%.

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##### Citations

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##### References

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##### Frequently Asked Questions (16)

###### Q2. What are the contributions mentioned in the paper "A gate-level leakage power reduction method for ultra-low-power cmos circuits†" ?

In order to overcome this, the authors propose a design technique that can be used during logic design in order to reduce the leakage current and power. The authors demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54 % for some circuits.

###### Q3. What is the effect of a lower supply voltage on the circuit?

Propagation delays through logic gates increase as the supply voltage decreases, and the overall noise immunity of the circuit decreases.†

###### Q4. What is the effect of low threshold voltages on the circuit performance?

For circuits with very low threshold devices, the standby (leakage) power is no longer negligible [1] and can even dominate the active and short-circuit power.

###### Q5. What is the case for a combinational circuit?

since the combinational circuit being analyzed is assumed to be part of a sequential network, the latches in the sequential network can be easily modified to force either a 0 or 1 during sleep mode.

###### Q6. What is the impact of high power consumption on portable devices?

High power consumption also impacts battery-powered portable devices by requiring either large battery packs or unacceptably short operating time.

###### Q7. What is the purpose of this paper?

In this paper, the authors propose a novel design method that can be used during logic design in order to reduce the leakage power of CMOS circuits.

###### Q8. What is the way to calculate the leakage of a combinational circuit?

A circuitlevel simulator, such as SPICE, can be used to do this, but a more efficient solution is possible since the leakage depends only on the steady state node values.

###### Q9. How is the power dissipation of a VLSI device?

It is well known that the power dissipation is directly proportional to the square of the power supply voltage, while it is proportional only to the first power of the capacitance and frequency (Pav = CV 2f).

###### Q10. What is the way to estimate the leakage of a large combinational circuit?

In order to efficiently estimate the leakage of a large combinational circuit for a given input pattern, the authors need to develop models for logic gates that give the leakage current drawn by the gate for each of its input patterns.

###### Q11. How do the authors change the logic design of a CMOS circuit?

Using minimal additional circuitry, the authors propose to modify the logic design so that whenever a circuit is put in standby, its internal state is set to a lowleakage state, preferably the lowest-leakage state possible.

###### Q12. What is the way to determine the leakage of a combinational circuit?

Consider a combinational circuit whose input nodes are state bits of an overall sequential circuit which will be put in standby mode.

###### Q13. What is the difficult problem to solve?

The “search problem” for the vector that gives the least leakage power is a very difficult one because of the potentially huge size of the search space.

###### Q14. How do the authors determine the leakage current for a given input pattern?

Using a circuit-level simulator, such as SPICE, and an appropriate MOSFET device model, the authors determine the leakage current for each input pattern and log the results into a look-up table.

###### Q15. What is the way to estimate the leakage of a combinational circuit?

The search algorithm for a low-leakage input vector, to be given in section 4, depends on being able to estimate the leakage for a candidate vector.

###### Q16. How can one force a value during sleep mode?

other types of latches and flip-flops can also be modified in similar ways to force appropriate values during sleep mode.