Proceedings ArticleDOI
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation
Mário P. Véstias,Horácio C. Neto +1 more
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TLDR
This paper proposes a generic NoC architecture that can be tailored to the specific requirements of the system looking to improve area usage, average communication latency and throughput and an extensive analysis and tests of the proposed architecture have been performed.Abstract:
The design of electronic systems in a System-on-Chip (SoC) depends on the reliable and efficient interconnection of many different components. The Network-on-Chip (NoC) is a scalable communication infrastructure able to tackle the communication needs of future SoC. However, routers of a NoC introduce a relative area overhead and increase the average latency. Therefore, in the design process it is important to consider mechanisms to improve area and performance of NoC infrastructures. In this paper, we propose a generic NoC architecture that can be tailored to the specific requirements of the system looking to improve area usage, average communication latency and throughput. An extensive analysis and tests of the proposed architecture have been performed to evaluate the approach.read more
Citations
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Proceedings ArticleDOI
FPGA based design of low power reconfigurable router for Network on Chip (NoC)
TL;DR: Results show that the proposed design consumes less power compared to the previously designed reconfigurable routers, and power dissipation of the proposed reconfigured router is reduced using Power gating technique.
Proceedings ArticleDOI
A link removal methodology for Networks-on-Chip on reconfigurable systems
TL;DR: A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount and can save 30% of the hardware amount without performance degradation in the image recognition application susan.
Proceedings ArticleDOI
A Temporal Correlation Based Port Combination Methodology for Networks-on-Chip on Reconfigurable Systems
TL;DR: A temporal correlation based port combination algorithm that customizes the router design in network-on-chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount.
Proceedings ArticleDOI
A Dynamic Link-Width Optimization for Network-on-Chip
TL;DR: This paper proposes to dynamically adjust link-width of each port on a router optimized to spatially biased traffic to achieve a dynamical link- width optimization at run-time.
Journal ArticleDOI
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs
TL;DR: A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount.
References
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Journal ArticleDOI
Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
Proceedings ArticleDOI
A generic architecture for on-chip packet-switched interconnections
Pierre Guerrier,Alain Greiner +1 more
TL;DR: This paper presents an architectural study of a scalable system-level interconnection template, and discusses the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services.
Proceedings ArticleDOI
Bandwidth-constrained mapping of cores onto NoC architectures
Srinivasan Murali,G. De Micheli +1 more
TL;DR: NMAP is presented, a fast algorithm that maps the cores onto a mesh NoC architecture under bandwidth constraints, minimizing the average communication delay, and the NMAP algorithm is presented for both single minimum-path routing and split-traffic routing.
Proceedings Article
Network on Chip : An architecture for billion transistor era
Ahmed Hemani,Axel Jantsch,Shashi Kumar,Adam Postula,Johnny Öberg,Mikael Millberg,Dan Lindqvist +6 more
TL;DR: Looking into the future, when the billion transitor ASICs will become reality, this paper presents Network on a chip (NOC) concept and its associated methodology as a solution to the design productivity problem.
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