A graph theoretic approach to minimize total wire length in channel routing
15 Oct 2003-Vol. 1, pp 414-418
TL;DR: This work develops a purely graph theoretic framework, designated as TAH (track assignment heuristic), for computing routing solutions using the minimum possible area for two-layer no-dogleg routing solutions for most of the well-known benchmark channels.
Abstract: Minimization of total (vertical) wire length in VLSI physical design automation is one of the most important topics of current research. As fabrication technology advances, devices and interconnection wires are placed in closer proximity and circuits operate at higher frequencies. At the same time, delay is a factor that suspends a desired signal in conveying it to its destination in a proper time. This factor is directly proportional to the length of the interconnecting wire segments involved (Pal, R. K., "Multi-Layer Channel Routing: Complexity and Algorithms", Narosa Pub. House, 2000). Pal et al. (see Proc. 8th VSI/IEEE Int. Conf. on VLSI Design, p.202-7, 1995) developed a purely graph theoretic framework, designated as TAH (track assignment heuristic), for computing routing solutions using the minimum possible area. We compute routing solutions with reduced total wire length using the TAH framework. The algorithm is used for computing two-layer no-dogleg routing solutions for most of the well-known benchmark channels. The performance of our algorithm is highly encouraging.
Citations
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01 Jan 2014
TL;DR: Performance of the algorithms is encouraging enough for most of the existing benchmark channels, and reduction in crosstalk for these channels is up to 28.34% for a given routing solution.
Abstract: With the advancement of fabrication technology, devices and interconnecting wires are being placed in closer proximity and circuits are operating at higher frequencies. This results in crosstalk between overlapping wire segments. Work on routing channels with reduced crosstalk is a very important area for current research. The crosstalk minimization problem in the reserved two-layer Manhattan routing model is NP-complete, even if the channel instances are without any vertical constraints. The problem of crosstalk minimization remains NP-complete for general instances of channel specifications with both horizontal and vertical constraints. In this paper we have developed two algorithms for computing reduced crosstalk routing solutions on a given routing solution of minimum area for general instances of channel specifications. Performance of our algorithms is encouraging enough for most of the existing benchmark channels, and reduction in crosstalk for these channels is up to 28.34% for a given routing solution.
6 citations
Cites background from "A graph theoretic approach to minim..."
...cost optimization criterion in routing a channel [4], [12], [14], [19], [20] followed by wire length minimization [10], [16], [18]....
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TL;DR: Two heuristic algorithms to reduce the total (vertical) wire length in channel routing problem in the reserved multi-layer no-dogleg Manhattan routing models, where vertical and horizontal layers of interconnect alternate.
Abstract: The minimization of total wire length is one of the most key issue in VLSI physical design automation, as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delay. So, it is still important as cost as well as high performance issue. The problem of reduced wire length routing solutions in no-dogleg reserved two-layer (VH) and multi-layer (ViHi, 2 ≤ i < dmax and ViHi+1, 2 ≤ i < dmax − 1) channel routing is NP-hard, so, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. Here we propose two algorithms to reduce the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop an algorithm Multi-Layer_Reduced_Wire_Length (MLRWL) to minimize the total (vertical) wire length in channel routing problem in the reserved multi-layer (ViHi, 2 ≤ i < dmax and ViHi+1, 2 ≤ i < dmax − 1) no-dogleg Manhattan routing models, where vertical and horizontal layers of interconnect alternate. Experimental results computed for available benchmark instances indicate that the algorithms perform well. Keywords—Channel routing problem, Manhattan routing, No-dogleg, Parametric difference, Wire length minimization, VLSI.
1 citations
Cites background or methods from "A graph theoretic approach to minim..."
...for wire length minimization [8], and algorithm Modified_Track_Assignment_Heuristic (MTAH) for wire length minimization [11]....
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...have been developed for computing area and/or wire length minimization in two-layer no-dogleg Manhattan channel routing model [8,9,11]....
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...Generally, a channel is a rectangular routing region between circuit blocks having two parallel rows of fixed terminals on a chip floor [1-3,5-14]....
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...In literature, only a very few algorithm have been devised for minimizing total wire length of the channel [2,3,8,9,11,12]....
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16 Jul 2014
TL;DR: This paper develops two heuristic algorithms to minimize the total (vertical) wire length in channel routing problem and develops an efficient re-router Further_Reduced_Wire_Length to optimize the wirelength in the reserved two-layer (VH) no-dogleg channel routing model.
Abstract: In VLSI physical design automation minimization of total (vertical) wire length is one of the most important problems as it reduces the cost of physical wiring required along with the electrical hazards of having long wires in the interconnection, power consumption, and signal propagation delays. Since the problem of computing minimum wire length routing solutions in no-dogleg reserved two- and four-layer channel routing is NP-hard, it is interesting to develop heuristic algorithms that compute routing solutions of as minimum total (vertical) wire length as possible. In this paper we develop two algorithms to minimize the total (vertical) wire length in channel routing problem. First we develop an efficient re-router Further_Reduced_Wire_Length (FRWL) to optimize the wire length in the reserved two-layer (VH) no-dogleg channel routing model and then we develop a next algorithm Four_Layer_Reduced_Wire_Length (FLRWL) to optimize the total (vertical) wire length in the reserved four-layer (VHVH) no-dogleg Manhattan routing model. Experimental results computed for available benchmark instances are greatly encouraging.
1 citations
Cites background or methods from "A graph theoretic approach to minim..."
...Most of the algorithms have been developed for area minimization of a channel [1-2,5-6,9-10,14] and only a few have been concentrated on wire length minimization [3,8-12]....
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...As already mentioned that most of the channel routing algorithms in literature have been developed for area minimization and only a very few have been devised for minimizing total wire length of the channel [1-3,5-14]....
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Proceedings Article•
01 Jan 2010TL;DR: An algorithm which is capable of transforming a gridded dogleg channel routing problem into a constraint programming (CP) problem, which has the potential to be used in dealing with other routing problems in VLSI physical design automation.
Abstract: In this article, we present an algorithm which is capable of transforming a gridded dogleg channel routing problem into a constraint programming (CP) problem. The transformed CP problem consists of a set of variables and a list of constraints; it can be solved by JaCoP, a finite-domain constraint programming solver. For a given dogleg channel routing problem, our approach is able to minimize the number of tracks and the number of vias. Although the transformed CP problems cannot be solved in polynomial time, optimal results can be found efficiently for small to medium cases. Moreover, for large cases, suboptimal results can be generated in exchange for significantly reduced execution time. As constraint programming technologies advance (e.g., parallel constraint programming), the execution time of the proposed approach can be improved. Additionally, our approach has the potential to be used in dealing with other routing problems in VLSI physical design automation.
1 citations
Cites background from "A graph theoretic approach to minim..."
...Keywords: Dogleg Channel Routing, VLSI Physical Design Automation, Constraint Programming...
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01 Oct 2007
TL;DR: This paper has developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions.
Abstract: Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.
Cites methods from "A graph theoretic approach to minim..."
...As a consequence, several two-layer heuristic algorithms for computing minimum area channel routing solutions have been proposed in last three decades [1,2,6,10] (and many others), and a very few work in minimizing wire length has been done in the RLMR model [4,7,8,9]....
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References
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28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
655 citations
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.
539 citations
"A graph theoretic approach to minim..." refers background in this paper
...One of the most important routing strategies is channel routing [6, 8 ]....
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...As a consequence, several two-layer channel routing heuristic algorithms for computing minimum area routing solutions have been proposed in last three decades [2,3, 8 ], and a very few work in minimizing wire length has been done in the reserved layer Manhattan routing model [6]....
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...the horizontal constraint graph (HCG) and the vertical constraint graph (VCG) [6, 8 ]....
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TL;DR: It is shown that track-oriented greedy algorithms can be modified to solve other channel routing problems, and modified algorithms have good performance and show strong potential to outperform existing algorithms.
Abstract: A general approach for the channel routing problem is presented as a framework for a class of heuristic routing algorithms. The algorithm is shown to possess a backtracking capability that increases the chance of completing the routing with a minimum number of tracks. Since the concepts described are general, they can be applied to other channel problems, such as switchbox routing, three-layer routing, and multilayer routing, or even to the overlap model, with only a few modifications. It is shown that track-oriented greedy algorithms can be modified to solve other channel routing problems. As examples, the algorithm is modified to solve the Manhattan switch-box problem and channel routing problems in the overlap and knock-knee models. Preliminary results show that the modified algorithms have good performance and show strong potential to outperform existing algorithms. Applying the algorithm MCRP-ROUT to the benchmark Deutsch's difficult problem and Burstein's difficult problem, routing solutions of 19 tracks and six tracks, respectively, were obtained. >
53 citations
Book•
29 Apr 2000
TL;DR: This work states that a general framework for Track Assignment in Multi-Layer Channel Routing and an Efficient Algorithm for Finding a Lower Bound on the Area of Routing are needed.
Abstract: Foreword / Preface / Introduction / Literature Survey / Resolving Horizontal Constraints in Multi-Layer Channel Routing / A General Framework for Track Assignment in Multi-Layer Channel Routing / Computational Complexity of Area Minimization in Multi-Layer Channel Routing and an Efficient Algorithm / An Algorithm for Finding a Lower Bound on the Area of Routing / Computational Complexity of Wire Length Minimization in Channel Routing / Algorithms for Minimizing Wire Length in Multi-Layer Channel Routing / Summary, Related Fields of Research and Open Problems / A. Channel Specifications / B. Tables for Reduced Wire Length / Bibliography / Subject Index.
33 citations
04 Jan 1995
TL;DR: A general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle is proposed and an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models is designed.
Abstract: In this paper we propose a general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle. Within this framework we propose algorithms for computing routing solutions using optimal or near optimal number of tracks for several well-known benchmark channels in the two-layer VH. Three-layer HVH, and multi-layer V/sub i/H/sub i/ and V/sub i/H/sub i+1/ routing models. Within the same framework we also design an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models.
20 citations