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A heuristic algorithm for via minimization in VLSI channel routing

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TLDR
This paper uses heuristic technique to find the maximum independent set of a graph with polynomial time complexity in VLSI channel routing with movable terminal and shows the experimental results and hardcopy solutions of some channel instances to prove the efficiency of this approach.
Abstract
We know that via minimization is a very important problem in channel routing. The main aim of via minimization is to improve the circuit performance and productivity, to reduce the completion rate of routing and also to fabricate integrated circuit correctly. In this paper, we are using a heuristic algorithm for solving via minimization problem in VLSI channel routing with movable terminal. Here we concentrate on how fast we find out maximum independent set from the net intersection graph. That is why here we use heuristic technique to find the maximum independent set of a graph with polynomial time complexity. Next, we show how to use that maximum independent set to solve the via minimization problem using an example. Then, we show the experimental results and hardcopy solutions of some channel instances to prove the efficiency of this approach.

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Journal Article

An efficient approach to constrained via minimization for two-layer VLSI routing

TL;DR: In this article, a new approach is proposed for two-layer VLSI routing, which is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
References
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Journal ArticleDOI

Minimum-Via Topological Routing

TL;DR: This paper describes the topological routing algorithm in detail, based on a circle graph representation of the net intersection information of the routing problem, which selects a maximal set of nets that can be routed without vias.
Journal ArticleDOI

An Unconstrained Topological Via Minimization Problem for Two-Layer Routing

TL;DR: It is shown that the simplest problem of this type is NP-complete and a heuristic algorithm for topological via minimization is proposed and proposed.
Journal ArticleDOI

A new approach to topological via minimization

TL;DR: A two-chain maximum dominance problem, which is of interest in its own right, is considered, and its applications to other very large-scale integration layout problems are shown.
Journal ArticleDOI

Optimal Wiring of Movable Terminals

TL;DR: This paper considers the problem of local wiring in a VLSI chip and is able to find polynomial time optimal algorithms while, for others, it proves NP-completeness and suggest efficient heuristics.
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