Abstract — A digital-to-time converter (DTC) controls time delay by a digital code,
which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-
interleaved ADC. This paper proposes constant-slope charging as a method to realize a
DTC with intrinsically better integral non-linearity (INL) compared to the popular
variable-slope method. The proposed DTC chip realized in 65nm CMOS consists of a
voltage-controlled variable-delay element (DTC-core) driven by a 10-bit digital-to-
analog converter. Measurements with a 55MHz crystal clock demonstrate a full-scale
delay programmable from 19ps to 189ps with a resolution from 19fs to 185fs. As
available oscilloscopes are not good enough to reliably measure such high timing
resolution, a frequency-domain method has been developed that modulates a DTC edge
and derives INL from spur strength. An INL of 0.17% at 189ps full-scale delay and 0.34%
at 19ps are measured, representing 8-9 bit effective INL-limited resolution. Output rms
jitter is better than 210fs limited by the test setup, while the DTC consumes 1.8mW.
Index Terms — digital-to-time converter, DTC, integral nonlinearity, INL, phase-
locked loop, PLL, constant slope, variable slope, delay, variable delay, delay
measurement.
===================================================================
A High-Linearity Digital-to-Time Converter
Technique: Constant-Slope Charging
Jiayoon Zhiyu Ru
1,2
, Claudia Palattella
1
, Paul Geraedts
1,3
, Eric Klumperink
1
, Bram Nauta
1
1
University of Twente, Enschede, Netherlands
2
now with Qualcomm
3
now with Teledyne Dalsa
zhiyu.ru@gmail.com
1
I. INTRODUCTION
Time delay is often defined as the time difference between the threshold-crossing points of
two clock edges. If delay is programmable by a digital code, a digital-to-time converter
(DTC) results. It is a basic building block suitable for several applications, e.g. fractional-N
phase-locked loops (PLL) [1]-[4], (sub-)sampling oscilloscopes [5][6], automatic test
equipment (ATE) [7], direct digital frequency synthesis (DDFS) [8], polar transmitter [9],
radar [10], phased-array system [11], and time-interleaved ADC timing calibrations [12]. This
paper aims at improving the time resolution and linearity of a DTC. A nominal full-scale
delay in the order of 100ps is targeted with fine delay steps of less than 100fs.
The basic element of a DTC is a variable-delay element, and there are different ways to
implement delay in CMOS. A distributed circuit such as an ideal transmission line can
theoretically provide true time delay while keeping the waveform undistorted. However, it
requires unpractically long line length in CMOS technology (e.g. 100ps × 2·10
8
m/s = 20mm).
Moreover, as CMOS interconnect losses are high and frequency dependent, different
amplitudes and waveforms result at different delay tap-points along a transmission line, which
introduces zero-crossing variations when sensed by a comparator [13]. Lumped circuits such
as all-pass filters can approximate a true time delay compactly [14][15] and maintain signal
waveform, but noise and dynamic range are compromised.
If the waveform is not important and delayed clock generation is the purpose, digital
circuits can be used. Minimum digital gate delays are on the order of 10ps in 65nm CMOS.
However, if the difference between two gate delays is used, or if the gate delay is tunable,
much smaller delay steps can be realized, for example in the order of 100fs as will be
presented in this work. Although the absolute delay is still limited by the intrinsic gate delay,
the relative delay steps can be much smaller.
2
If delay tuning is linear, a high-linearity DTC can be realized. A linear DTC is favored, as
calibration of only two points is sufficient, in contrast to a non-linear DTC that require multi-
point calibration [16]. To characterize linearity, integral nonlinearity (INL) is an important
metric for a DTC, similar to digital-to-analog converters (DAC). Non-zero DTC INL limits
the achievable spur level in fractional-N PLLs [1]-[3] [16] and the timing accuracy in
sampling oscilloscopes.
A DTC often exploits a voltage ramp generated by a current source charging a capacitor,
and a comparator with threshold voltage V
d
defining a time delay t
d
(see Fig. 1). Switched
capacitors [1][2][4] or switched current sources [3][6][7] can be applied to program delay.
These approaches produce a delay by varying the slope from one ramp to another, which we
refer to as the variable-slope method (see Fig. 2a). Using this method, 300fs delay resolution
has been achieved in [2]. However, high resolution does not necessarily mean high linearity.
In this paper, we propose a constant-slope method in which all ramps ideally would have the
same slope, in contrast to the variable-slope method (see Fig. 2b). To still realize variable
delay, a variable start voltage is used which can linearly program delay. We will show that
this method is intrinsically more linear, allowing for a more linear DTC than variable slope
offers. Before we do this in the next section, we first briefly discuss related previous work.
In [17], the nonlinearity of the variable-slope method was observed but not explained. The
use of a high-gain comparator to improve INL was proposed in [17], but no measurement
results were reported.
In [5] , delay is controlled by tuning the threshold voltage of a comparator, which would
result in linear delay control if the slope of the ramp does not change over the threshold tuning
range. Practically this is challenging, as the current produced by a current source as shown in
Fig. 1 depends on the voltage across it, and hence on the capacitor voltage V
C
. Moreover, the
3
comparator in [5] works at varying common-mode voltage, leading to a variable speed of the
comparator, i.e. an extra INL source.
Another way to realize variable delay is by phase interpolation, which can be implemented
using current sources [18][19], resistors [20][21] or delay lines [22]. The basic concept of
interpolation and example waveforms are shown in Fig. 3, where the middle parts are
constant-slope, assuming V
A
and V
B
have the same slope. However, phase interpolation is
functionally different as it requires two edges to be present, between which it can place a new
edge. In contrast, this work aims to produce a delayed edge after one incoming critical edge
that triggers one charging process.
The main new contributions of this paper are threefold: 1) a concept to define a constant-
slope method and to identify its fundamental advantages in terms of INL compared to a
variable-slope method; 2) a new circuit topology in which the start voltage controls the delay
of only one critical edge, leading to high linearity and low jitter; 3) measurement results
demonstrating a fine resolution and a small INL, for which a new measurement method was
devised.
This paper is organized as follows: section II explains the constant-slope method and its
advantage in linearity; section III describes the design of a DTC circuit using this method;
section IV presents measurements and section V conclusions.
II. CONSTANT-SLOPE METHOD
A. Constant-Slope Ramp Generation
To generate a voltage ramp with a controlled slope (S=∆v/∆t), often a current is used to
charge a capacitor as shown in Fig. 1, where S=I/C. The delay time (t
d
) of this ramp from
zero voltage to the voltage V
d
is:
4
=
/
(1)
As shown by (1), if we want one variable to control delay, we can either vary the slope S
(“variable slope”) at fixed voltage V
d
, or keep the slope fixed and vary voltage V
d
. In practice,
however, a single ramp often has a changing slope as shown in Fig. 1(b), therefore varying V
d
does not always give a linearly-controlled delay.
Instead, we can vary the start-voltage V
st
as shown in Fig. 4 between 0 and V
st,max
. To
generate a linearly-controlled delay, it is sufficient if the part below V
st,max
is constant-slope,
while for the part above V
st,max
it suffices to have a constant-shape
1
. As the trajectory above
V
st,max
is shared for all ramps and adds a fixed amount of delay, it does not affect the linearity
of the delay control function. Similarly, the same ramp start-up behavior between t
0
and t
1
adds a delay offset to all ramps which does not hurt linearity either.
A constant-shape above V
st,max
ensures that at different V
d
, the delay τ between two ramps
keeps constant, and it also renders INL benefits as described below.
B. Advantage of Constant-Slope Method on INL
We will use simple models to gain intuitive understanding. The delay function in Fig. 2
contains two distinct actions: 1) ramp generation and 2) threshold comparison. The ramp
generation produces a ramp with controlled slope, while the threshold comparison defines a
decision threshold V
d
and produces an output edge when crossing the threshold. The variable-
slope-induced INL comes from the behavior of a practical comparator.
One source of delay INL is the comparator bandwidth limit, which can be modeled by
adding an RC network at the comparator output. It can be derived that, in case of an input
ramp signal, the propagation delay of an RC network of any order contains nonlinear
functions of the input ramp time [23][24], e.g. exponential and logarithmic functions.
1
Being constant-shape between two ramps is equivalent to having the same (local) slope at equal ramp voltage. This property allows for
an alternative but important interpretation of the name “constant slope”, namely that the (local) slope is constant when comparing ramps of
different delay settings at equal ramp voltage.
5
