# A high performance architecture for rotating decimal coordinates

## Summary (2 min read)

### Introduction

- Numbers are commonly expressed by human beings using decimal representation; as a consequence, in the early days of computing, most of the first computers worked with decimal operands [1].
- The need for high precision engineering and manufacturing systems is also essential in CAD/CAM.
- Originally, CORDIC was applied to binary arithmetic, but later its application was proposed for decimal data [13], [14].
- Finally, in section V, the conclusions are given.

### A. Reviewing the binary CORDIC method

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- Walther [16] extended the method to hyperbolic and linear coordinates.
- In vectoring mode, the vector (x0, y0) is progressively rotated towards the x-axis by means of angles such as those previously mentioned, so that the component y approaches 0.

### B. Reviewing the Decimal CORDIC Method

- These devices usually work with numbers in decimal format and, therefore, binary CORDIC cannot be directly used.
- The drawback of this decimal CORDIC method lies on the relation between any two consecutive elementary angles in the form tan-1(10-j).
- This fact facilitates convergence in binary CORDIC, as expressed in (5).
- Therefore, the advantages of using the algorithm with BCD operands would be reduced to omit conversion between BCD and binary representation and, consequently, to avoid loss of precision.

### III. THE NEW DECIMAL CORDIC METHOD

- The proposal for a new decimal CORDIC method is based on the selection of successive angles αj such that: αj = tan-1(z⎣j⎦) (10) where z⎣j⎦ is the value resulting from truncating zj after the first digit on the left different from 0.
- The computation of the factor for compensating this scaling can be obtained by means of the following expression: KND-1 = ∏j = 0..n cos(tan-1(z⎣j⎦)) (15) In Table V, the values for the scaling compensation factor incorporated within the first iterations are shown.
- 6 LUT would constitute the storage block for tx,0, other 6 LUT would compound the LUT block for tx,1, and so Therefore, each small LUT will receive as inputs the value of a single digit of the coordinate and the mantissa and exponent of z⎣j⎦ .

### A. Some Details on the Architecture Implementation

- Addition on BCD operands is more complex than binary addition since the carry resulting from the sum of two digits must be propagated to the sum of the following ones [13].
- BCD X3 representation allows decimal addition/subtraction to be more efficiently performed, since only two 4-bit binary adders are required for each pair of digits.
- The final result is directly obtained in BCD X3.
- Conversion from BCD to BCD X3 requires only 10 gates distributed over 3 level, and similar resources are needed when transforming BCD X3 into BCD operands.
- The complete architecture for each of the iterations of the proposed ND-CORDIC method is shown in Fig 1.

### B. Experiments on Precision

- Different tests were carried out so as to make a complete comparison with regard to precision between B-CORDIC, DCORDIC, and the ND-CORDIC method proposed in this work.
- Values within the range [0, 1) were chosen for the (x, y) coordinates and also for the rotation angle θ.
- For DCORDIC and ND-CORDIC, a conversion stage from BCD to BCD X3 was included, whereas for B-CORDIC the BCD operands were converted into binary numbers.
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- The error decreases much faster for ND-CORDIC.

### C. Experiments on Latency and Hardware resources

- The proposed architecture was implemented on VHDL using the Xilinx ISE 7.1i tool.
- The global method was implemented on an unfolded architecture.
- A homogeneous length of 28 bits was used for every number format, so six fractional digits, corresponding to 24 bits, were considered for the BCD original numbers.
- The results for the delays and the FPGA resources used, when considering a single iteration and including number format conversions and scaling compensation, are shown in Table VI for comparison.
- It can be observed that ND-CORDIC offers better global performance than D-CORDIC and B-CORDIC for the considered iterations.

### V. CONCLUSIONS

- One of the most important tasks in new hardware design is to achieve high performance rates with a trade-off between precision and delays of the circuitry that forms these new embedded architectures.
- It seems that there is a growing trend towards developing new systems integrating decimal arithmetic, which is required in many practical research areas.
- Moreover, the maximum error obtained is always lower for the proposed method than for binary and decimal CORDIC.
- At this point, new scaling compensation techniques must be studied and developed so as to improve delay and resources utilization.
- This work has been supported by the Generalitat Valenciana under Grant No. GV/2007/173.

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##### References

^{1}

2,639 citations

### "A high performance architecture for..." refers background or methods in this paper

...In B-CORDIC, compensation without products is easy to perform due to the fact that the scale factor is a constant [12]....

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...CORDIC was developed by Volder [12] for computing the rotation of a 2D vector of circular coordinates expressed as binary numbers, exclusively using addition and shift operations....

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...1757978-1-4244-1666-0/08/$25.00 '2008 IEEE CORDIC was developed by Volder [12] for computing the rotation of a 2D vector of circular coordinates expressed as binary numbers, exclusively using addition and shift operations....

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...CORDIC (COordinate Rotation Digital Computer) is a relevant method to approximate mathematical functions [12]....

[...]

^{1}

1,044 citations

### "A high performance architecture for..." refers background or methods in this paper

...Walther [16] extended the method to hyperbolic and linear coordinates....

[...]

...The elementary angles αj must fulfil the following condition [16]:...

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...Indeed, convergence can be achieved by repeating certain iterations [16], as shown in Table I....

[...]

304 citations

### "A high performance architecture for..." refers methods in this paper

...Several methods to avoid performing the final product by Km and carry out the scaling compensation in parallel with each of the iterations have been proposed [17]-[20]....

[...]

287 citations

### "A high performance architecture for..." refers background in this paper

...If the different BCD X3 digits of xj are considered, the term tx0 can be expressed as: tx,0 = (xj[5] xj[4] xj[3] xj[2] xj[1] xj[0]) cos(tan(z⎣j⎦)) (21)...

[...]

...In spite of that, some examples of decimal architectures can be found, such as Hewlett Packard [2], Texas Instruments [3] and Casio calculators [4], and some others [4]....

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160 citations

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##### Frequently Asked Questions (2)

###### Q2. What have the authors stated for future works in "A high performance architecture for rotating decimal coordinates" ?

As a future work, an interesting task consists in developing a hardware implementation of a specific CORDIC-based rotator embedded on a decimal architecture.