Journal ArticleDOI
A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs
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TLDR
A column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors and error correction scheme to improve the linearity is proposed.Abstract:
This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.read more
Citations
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Journal ArticleDOI
A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel $\Delta \Sigma$ ADC Architecture
Youngcheol Chae,Jimin Cheon,Seung-Hyun Lim,Minho Kwon,Kwi-sung Yoo,Wun-ki Jung,Dong Hun Lee,Seogheon Ham,Gunhee Han +8 more
TL;DR: A 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture with second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well.
Journal ArticleDOI
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs
Hyeon-June Kim,Sun-Il Hwang,Ji-Wook Kwon,Dong-Hwan Jin,Byoung-Soo Choi,Sang-Gwon Lee,Jong-Ho Park,Jang-Kyoo Shin,Seung-Tak Ryu +8 more
TL;DR: This paper presents a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties and can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance.
Journal ArticleDOI
Column-Parallel Digital Correlated Multiple Sampling for Low-Noise CMOS Image Sensors
TL;DR: In this article, a low-noise CMOS image sensor using column-parallel high-gain signal readout and digital correlated multiple sampling (CMS) is presented.
Journal ArticleDOI
A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors
TL;DR: The Forward Error Correction (FEC) of the pDAC improves its robustness against device mismatch and performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory.
Journal ArticleDOI
Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme
TL;DR: The power consumption of the column-parallel 11-bit two-step quantization scheme is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits.
References
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Book
Principles of Data Conversion System Design
TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Journal ArticleDOI
A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change
S. Yoshihara,Y. Nitta,Masaru Kikuchi,K. Koseki,Y. Ito,Yoshiaki Inada,S. Kuramochi,Hayato Wakabayashi,M. Okano,H. Kuriyama,J. Inutsuka,A. Tajima,T. Nakajima,Y. Kudoh,Fumihiko Koga,Y. Kasagi,S. Watanabe,Tetsuo Nomoto +17 more
TL;DR: A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS image sensor fabricated in a 0.18-mum single-poly triple-metal (1P3M) process is described, which has 38% fill factor and 12ke-/lux sensibility.
Journal ArticleDOI
Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors
TL;DR: A CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC that can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals.
Proceedings ArticleDOI
High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor
Y. Nitta,Yoshinori Muramatsu,K. Amano,Takayuki Toyama,JunYamamoto,Koji Mishina,A. Suzuki,T. Taura,Akihiko Kato,M. Kikuchi,Y. Yasui,H. Nomura,Noriyuki Fukushima +12 more
TL;DR: A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process that implements digital double sampling with analog CDS on a column parallel ADC.
Journal ArticleDOI
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters
TL;DR: In this paper, a column-parallel cyclic 12-bit ADC array with column parallel cyclic ADCs and a global electronic shutter is presented for high-speed, high-sensitivity 512 times512 CMOS image sensor.