A High Speed, Low Energy Comparator Based on Current Recycling Approach
22 May 2021-pp 1-5
TL;DR: A high speed, low energy dynamic comparator using current recycling approach is proposed in this paper and the variations in latency is observed from 10 ps to 1 ns for working range of 1 V.
Abstract: A high speed, low energy dynamic comparator using current recycling approach is proposed in this paper. The current flowing through the preamplifier during the regenerative phase is sensed and added to the regenerative nodes for high speed operation. The increment in power is further compensated using additional clock signal to prevent the full discharge of output nodes of the preamplifier. The comparator is designed and simulated in UMC 180 nm CMOS process at 1.8 V power supply. The performance of comparator is verified at different process corners. The designed comparator operates at a frequency of 500 MHz and consumes 162 fJ of energy. The variations in latency is observed from 10 ps to 1 ns for working range of 1 V. The Monte Carlo simulations are performed for 200 samples resulting in a mean offset of-0.0056 mV and standard deviation of 7.42 mV.
Citations
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09 Aug 2021
TL;DR: In this paper, a low kickback noise and low power dynamic comparator is proposed, which uses the current recycling approach to save power and proposes two noise reduction techniques using only two additional switches.
Abstract: A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.
5 citations
01 Jan 2022
TL;DR: In this article , the primary SR latch-based comparator circuit using 180 nm standard CMOS is altered using 18 nm FinFET for even more significant speed in data comparison.
Abstract: Comparators are predominantly employed in data converters. In this paper, the primary SR latch-based comparator circuit using 180 nm standard CMOS is altered using 18 nm FinFET for even more significant speed in data comparison. The 18 nm FinFET technology produces energy-efficient conversion. 18 nm FinFET nodes have superior control over the channel, and they have quick switching speed and high current compared to CMOS. Cadence Virtuoso tool is utilized to design and simulate the circuit. The circuit works for high frequencies, even as much as 1 GHz. When compared to the original design, the speed in data conversion is escalated, providing better results.
DOI•
21 May 2023
TL;DR: In this paper , a single capacitor-based offset reduction technique for dynamic comparators is proposed, which uses only one capacitor and two transistors to reduce the offset introduced due to threshold mismatch, resulting in an energy efficient design.
Abstract: This work proposes a single capacitor-based offset reduction technique for dynamic comparators. It additionally uses only one capacitor and two transistors to reduce the offset introduced due to threshold mismatch, resulting in an energy-efficient design. The proposed technique reduces the offset by four to six times compared to the conventional design for the entire input range. The comparator is designed in 65 nm CMOS process using 1.2 V power supply. It occupies an area of $21.2\ \mu\mathrm{m}\times 16\ \mu\mathrm{m}$. The performance of comparator is verified using post-layout simulations. The maximum operating frequency of comparator is 2 GHz and it consumes 51 fJ of energy per conversion cycle. The Monte-Carlo simulations performed for 500 samples result in worst-case offset of 1.7 mV.
References
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18 Jun 2007
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Abstract: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time
587 citations
TL;DR: Measurements show that the dynamic bias comparator can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common-mode level of half the supply voltage.
Abstract: A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common-mode level of half the supply voltage.
105 citations
TL;DR: A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay.
Abstract: A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.
99 citations
TL;DR: An energy-efficient comparator design that achieves the highest reported comparator energy efficiency to the best of the authors' knowledge and greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay.
Abstract: This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting $g_{m}/I_{D}$ and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46- $\mu \text{V}$ input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.
99 citations
22 Dec 2009
TL;DR: In this article, a low-offset latched comparator using new dynamic offset cancellation technique is proposed, which achieves low offset voltage without pre-amplifier and quiescent current.
Abstract: A low-offset latched comparator using new dynamic offset cancellation technique is proposed. The new technique achieves low offset voltage without pre-amplifier and quiescent current. Furthermore the overdrive voltage of the input transistor can be optimized to reduce the offset voltage of the comparator independent of the input common mode voltage. A prototype comparator has been fabricated in 90 nm 9M1P CMOS technology with 152 µm2. Experimental results show that the comparator achieves 3.8 mV offset at 1 sigma at 500 MHz operating, while dissipating 39 μW from a 1.2 V supply.
63 citations