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Journal ArticleDOI

A K-Band High Power and High Isolation Stacked-FET Single Pole Double Throw MMIC Switch Using Resonating Capacitor

TL;DR: In this article, a K-band single pole double throw (SPDT) switch with low insertion loss, high isolation and ultra-high output power is demonstrated using 0.15-μm Gallium Arsenide (GaAs) technology.
Abstract: A K-band monolithic microwave integrated circuit (MMIC) transmit and receive (T/R) single pole double throw (SPDT) switch with low insertion loss, high isolation and ultra-high output power is demonstrated using 0.15- $\mu\text{m}$ Gallium Arsenide (GaAs) technology. A shunt field effect transistor (FET) configuration is used to provide low insertion loss and high isolation while the stacked-FET is employed to improve power handling capability. The novel GaAs switch exhibits a minimum measured insertion loss of 1.4 dB and less than 2.5 dB from 22 GHz to 26 GHz as well as 44 dB isolation. The measured input 1-dB power compression point $({P}_{1\, \mathrm{dB}})$ exceeds 4 W.

Summary (2 min read)

Introduction

  • (MMIC) transmit and receive (T/R) single pole double throw (SPDT) switch with low insertion loss, high isolation and ultrahigh output power is demonstrated using 0.15-m Gallium Arsenide (GaAs) technology.
  • The measured input 1-dB power compression point (P1dB) exceeds 4 Watts.
  • Parasitic cancelling switch was proposed in [6] to enhance isolation at Ka-band and 28.9 dB isolation was reported.

II. CIRCUIT DESIGN

  • Fig. 1 shows the configuration of the proposed dual shunt stacked-FET switch.
  • The transmitter (Tx) and receiver (Rx) arms are symmetrical.
  • Each arm consists of four pHEMTs to form a stacked-FET dual-shunt topology.
  • When the Tx arm is on (Tx and Common is a thru path), all the transistors Q1, Q2, Q3 and Q4 would be turned off by setting their bias voltage below the pinch-off value.
  • C1-C4 are the resonating capacitors which are employed in their novel design to enhance isolation.

A. Resonating capacitor for high isolation design

  • The key point to enhance the switch isolation is the use of dual-shunt topology.
  • During operation, the isolation port (bottom half of Fig. 2a) would be connected to the ground through a very small resistance.
  • At high frequency, the connecting transmission lines TL7, TL8 will dramatically change the impedance Zin. Fig. 2b shows the Zin for various lengths of TL7+TL8.
  • When the total length (TL7+TL8) is large, the isolation is degraded up to 30 dB and the insertion loss also increases (Fig. 2c).
  • In a stacked-FET layout (Fig. 4), the minimum required length of TL7 and TL8 is 200 µm to avoid the overlaps of two FETs and the input line and the top FET.

B. Stacked-FET Configuration

  • A major issue of GaAs MMIC switches is the power handling capability.
  • With the above analysis, the peak voltage swing across drain-gate and gate-source of each transistor will be VRF/4 and it swings around the DC bias voltage at the gate.
  • On the positive half cycle, if the gatesource voltage swing goes higher than the pinch-off voltage, Fig.3.
  • This optimal value of bias voltage is derived as _ 2 (2) Then, the maximum power for a given bias voltage is (3).
  • At high input power, the large voltage swing can make the gate-drain voltage to exceed the transistor breakdown voltage and cause device failures.

III. EXPERIMENTAL RESULTS

  • The resonating capacitors are realized by two metalinsulator-metal (MIM) cap in series.
  • DC supplies are provided through board traces which are wire-bonded to the chip DC pads.
  • The power measurement was performed with the input signal driven by a high power amplifier.
  • The switch exhibits less than 2.5 dB insertion loss, better than 10 dB return loss from 22 GHz to 26 GHz.
  • When the authors reverse the control signals of the SPDT switch, a similar response is recorded since the switch is symmetrical.

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Title
A K-Band High Power and High Isolation Stacked-FET Single Pole Double Throw MMIC Switch
Using Resonating Capacitor
Permalink
https://escholarship.org/uc/item/8jf644fg
Journal
IEEE Microwave and Wireless Components Letters, 26(9)
ISSN
1531-1309
Authors
Nguyen, DP
Pham, AV
Aryanfar, F
Publication Date
2016-09-01
DOI
10.1109/LMWC.2016.2597235
Peer reviewed
eScholarship.org Powered by the California Digital Library
University of California

A K-Band High Power and High Isolation Stacked-FET Single Pole
Double Throw MMIC Switch Using Resonating Capacitor
Duy P. Nguyen, Student Member, IEEE, Anh-Vu Pham, Senior Member, IEEE
and Farshid Aryanfar
Abstract — A K-band monolithic microwave integrated circuit
(MMIC) transmit and receive (T/R) single pole double throw
(SPDT) switch with low insertion loss, high isolation and ultra-
high output power is demonstrated using 0.15-m Gallium
Arsenide (GaAs) technology. A shunt field effect transistor
(FET) configuration is used to provide low insertion loss and
high isolation while the stacked-FET is employed to improve
power handling capability. The novel GaAs switch exhibits a
minimum measured insertion loss of 1.4 dB and less than 2.5 dB
from 22 GHz to 26 GHz as well as 44 dB isolation. The measured
input 1-dB power compression point (P
1dB
) exceeds 4 Watts.
Index Terms—T/R switch, stacked-FET, K-band, Gallium
Arsenide, MMIC.
I. INTRODUCTION
K-band systems have been found in variety of applications
such as: satellite, radar and digital point-to-point radio
services [1]. These systems demand a low loss, high isolation
and high power SPDT switches. Although PIN diode switches
can handle high power due to their high breakdown voltage
[2], they are not monolithically compatible with other devices
in a front-end module and consume high dc current. On the
other hand, GaAs MMIC switches are not only more
attractive in a fully integrated system but they also consume
very little DC power. A pseudomorphic high-electron-
mobility transistor (pHEMT) GaAs MMIC switch has a much
higher switching speed than the PIN diode one [3]. The major
issues of a GaAs T/R switch are low isolation at high
frequency and limited power handling capability due to the
gate-drain parasitic capacitance C
gd
and relatively low
breakdown voltage of the GaAs technology.
Several techniques have been introduced to improve GaAs
MMIC switch isolation and power handling capability. In [4],
authors used the ohmic-electrode-sharing technology for a
Ka-band switch; however, the design gives only 20.6 dB
isolation in a conventional series-shunt topology. The
impedance transformation switch was introduced in [5] to
improve the isolation to 30 dB. Parasitic cancelling switch
was proposed in [6] to enhance isolation at Ka-band and 28.9
dB isolation was reported. In all three designs, the power is
limited to only 21 dBm. A multiple stacked-FET switch was
introduced in [2,7] to enhance output power at high frequency.
In [2], a stacked metal–semiconductor field effect transistors
(MESFET) switch achieved 31 dBm output power but had
low isolation due to the increasing on-resistance.
In this paper, we present the design and development of a
novel dual shunt stacked-FET T/R switch. The switch
employed a stacked-FET topology to enhance power handling
capability and a resonating capacitor to achieve high isolation
Duy P. Nguyen and And-Vu Pham are with the Dept. of Electrical and
Comp. Engr., University of California, Davis, CA 95616 USA (e-mail:
dypnguyen@ucdavis.edu).
Farshid Aryanfar was with Samsung Research America, Richardson,
Texas, USA.
Fig. 1. Schematic diagram of the proposed stacked-FET switch
The switch fabricated in a 0.15-µm GaAs pHEMT process
TQP15 from Qorvo exhibits 2.5 dB insertion loss and better
than 44 dB isolation from 22 GHz to 26 GHz. The measured
input P
1dB
is 36 dBm over the frequency range. This is the
first time a resonating capacitor is used to enhance isolation of
a high power stacked-FET switch. To the best of our
knowledge, our proposed switch has the highest P1dB of all
reported GaAs MMIC switch at K-band.
II. C
IRCUIT DESIGN
Fig. 1 shows the configuration of the proposed dual shunt
stacked-FET switch. The transmitter (T
x
) and receiver (R
x
)
arms are symmetrical. Each arm consists of four pHEMTs to
form a stacked-FET dual-shunt topology. In the T
x
arm, the
transistor Q
1
is placed on top of Q
2
to form a stack connection.
A large resistor is put at the gate of each transistor to allow
some voltage swings at this node. Similar connections are
applied to Q
3
, Q
4
as well as the R
x
arm. When the T
x
arm is on
(T
x
and Common is a thru path), all the transistors Q
1
, Q
2
, Q
3
and Q
4
would be turned off by setting their bias voltage below
the pinch-off value. At the same time, Q
5
, Q
6
, Q
7
and Q
8
would be turned on to isolate the signal at the receiver arm.
C1-C4 are the resonating capacitors which are employed in
our novel design to enhance isolation.
A. Resonating capacitor for high isolation design
When a pHEMT is used in a switching application, it can
be modelled as a small resistor when being turned on (R
on
) or
a large capacitor when being turned off (C
off
). Fig. 2a shows
the equivalent circuit of Q3 and Q4 being turned off and Q7
and Q8 being turned on. The key point to enhance the switch
isolation is the use of dual-shunt topology. During operation,
the isolation port (bottom half of Fig. 2a) would be connected
to the ground through a very small resistance. The 90
o
TL16
transforms the low
impedance at point A in Fig. 1 to the high
impedance presenting at the common node while the 90
o
TL15 isolates the turned-off port from the leakage signal
coming from the common node to further reinforce the switch
isolation. Compared to the conventional series-shunt topology

Fig. 2. Switch equivalent circuit during operation (a); input impedance of the
turned off arm (b) and isolation with different TL lengths (c)
in [4,6], the isolation of our approach is increased by at least
15 to 20 dB. At high frequency, the connecting transmission
lines TL7, TL8 will dramatically change the impedance Z
in
.
Fig. 2b shows the Z
in
for various lengths of TL7+TL8. When
the input impedance looking into the transistor deviates from
the real axis, the isolation is significantly degraded. Fig. 2c
shows the simulated isolation of the circuit when the total
length of the TL7 and TL8 varies from 0 µm to 200 µm.
When the total length (TL7+TL8) is large, the isolation is
degraded up to 30 dB and the insertion loss also increases
(Fig. 2c). In a stacked-FET layout (Fig. 4), the minimum
required length of TL7 and TL8 is 200 µm to avoid the
overlaps of two FETs and the input line and the top FET. To
increase isolation, we propose to add a resonating capacitor
C
4
(C
4
= 0.3 pF in our design) to bring the impedance back to
the real axis (Fig. 2b). As a result, we can retrieve excellent
isolation and insertion loss in the frequency band of interests.
B. Stacked-FET Configuration
A
major issue of GaAs MMIC switches is the power
handling capability. The gate-drain breakdown voltage of the
0.15-µm GaAs FET is ~12 V which limits the maximum RF
voltage swing. We propose a stacked-FET configuration to
overcome this issue. Fig. 3 shows a stacked-FET
configuration which consists of two identical pHEMT
transistors with equal gate bias voltage and bias resistors.
Assume that the relative position of the gate to drain and gate
to the source are symmetrical; then C
gd
and C
gs
would be
equal and form a voltage divider at each transistor. If the gate
bias resistors are large enough to ensure adequate isolation
between the two gates, the voltage swing will be equally
divided between the two transistors. Therefore, the voltage
swing across C
gd1
, C
gs1
, C
gd2
and C
gs2
would be identical and
equal to the total RF voltage swing divided by 4 (Fig. 3).
Let’s denote the pinch off voltage, gate-drain breakdown
voltage and peak to peak RF voltage swing are V
pinch-off
, V
break-
down
and V
RF
,
respectively. With the above analysis, the peak
voltage swing across drain-gate and gate-source of each
transistor will be V
RF
/4 and it swings around the DC bias
voltage at the gate. On the positive half cycle, if the gate-
source voltage swing goes higher than the pinch-off voltage,
Fig.3. Stacked-FET configuration and voltage swing limitation
the FET will be gradually switched on and compression
occurs. On the negative half cycle, if the voltage swing goes
lower than the gate-drain breakdown voltage, compression
will also occur. The maximum voltage swing is then given by
|



|

4




(1)
For a depletion mode pHEMT process, V
bias
, V
pinchoff
and
V
breakdown
defined in (1) are negative values. Based on (1),
there is a value of V
bias
which can maximize the voltage swing
limitation. This optimal value of bias voltage is derived as
_



2
(2)
Then, the maximum power for a given bias voltage is
(3)
At high input power, the large voltage swing can make the
gate-drain voltage to exceed the transistor breakdown voltage
and cause device failures. To guarantee safe operations, the
typical bias voltage is chosen 1 V back-off from its optimal
value. From (3), when V
breakdown
= 12 V, V
pinch-off
=-1 V and
V
bias
= -5 V, the highest input power that the switch can handle
without any compression is 2.56 Watts. Hence, the P
1dB
is
expected to be 2 to 3 dB higher than this power level.
III. E
XPERIMENTAL
R
ESULTS
Fig. 4. Chip photo of the fabricated switch (2.6 mm x 1.2 mm)
The chip size is 2.6 mm x 1.2 mm. The transistor size is 720
m. Gate bias resistors are chosen to be 1 KΩ and are realized
on-chip. The resonating capacitors are realized by two metal-
insulator-metal (MIM) cap in series. Two lines TL14 and
TL16 in Fig. 1 are realized asymmetrically in the layout to
save the die area. Intensive electromagnetic (EM) simulation
was done to ensure the two transmission lines have equal
effective electrical length. The switch was measured using a
Keysight network analyzer PNA-X (N5247A) with on-wafer
probing and TRL calibration. DC supplies are provided
through board traces which are wire-bonded to the chip DC
pads. The power measurement was performed with the input
signal driven by a high power amplifier.

Fig. 5. Measured S-parameter at 
=0 V and Vg= -5 V
Fig. 6. Simulated versus measured insertion loss and isolation
Fig. 5 shows measured S-parameters of the proposed switch
at 
=0 V and Vg=-5 V. The minimum insertion loss is 1.4
dB at 24.5 GHz. The switch exhibits less than 2.5 dB insertion
loss, better than 10 dB return loss
from 22 GHz to 26 GHz.
Fig. 6 demonstrates the insertion loss and isolation of the
switch where the experimental results are compared to the full
wave electromagnetics simulated results. The measured
isolation is better than 44 dB from 22 GHz to 26 GHz.
Experimental results are well correlated with the simulated
ones in the frequency range. When we reverse the control
signals of the SPDT switch, a similar response is recorded
since the switch is symmetrical. When the bias voltage is
swept from -4 V to -6 V, small signal response is maintained
almost the same with a slight change in return loss.
Fig. 7 shows the output power and insertion loss of the
switch at 0 V/ -5 V gate bias and at 24.5 GHz. The switch
exhibits only 0.25 dB insertion loss degradation at 34 dBm
input power. The measured power agrees with our calculation
in (3). The measured input P
1dB
is 36 dBm. Similar
compression behaviour is also observed at 22 GHz and 26
GHz. Fig. 8 presents the compression behaviour of the switch
at 24.5 GHz at different bias conditions. The bias voltage V
g
=
-6 V gives the best response and the V
g
= -4 V gives the worst
response of all three as expected. Table I compares our work
with other GaAs MMIC switches at the same frequency range.
IV. C
ONCLUSION
We demonstrate a SPDT T/R MMIC switch using a dual-
shunt topology with a resonating capacitor stacked-FET
configuration in a 0.15-m GaAs process. Our experimental
results demonstrate 2.5 dB insertion loss, 44 dB isolation and
36 dBm input P
1dB
from 22 GHz to 26 GHz. Our switch has
the highest P
1dB
among all reported GaAs MMIC T/R switch
at K-band.
Fig. 7. Output power and insertion loss at 24.5 GHz and 0 V/-5 V bias
Fig. 8. Output power and insertion loss at 24.5 GHz and 0 V/-5 V bias
TABLE I
COMPARISON TO PREVIOUS WORK
Ref Freq
(GHz)
Ins. Loss
(dB)
Isolation
(dB)
P1dB
(dBm)
Chip size
(mm
2
)
[2] 21-27 2 20 30
4.47
[3] 20-40 2 25 23
1.61
[4] DC-60 1.64 20.6 21
0.55
[5] 38-45 2 30 19
2
[6] 18-28 3.1 28.9 NA
2.18
[8] DC-60 3 25 27.5
1
This work
22-26 2.5 44 36
3.12
R
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Citations
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Journal ArticleDOI
TL;DR: The envelope-tracking front-end module (ETFEM) consisting of an envelope- tracking supply modulator (ETSM), a dual-power-mode power amplifier (PA), and a single-pole-double-throw (SPDT) switch is proposed for the Long-Term Evolution-Advanced intraband carrier aggregation (CA) signal.
Abstract: The envelope-tracking front-end module (ETFEM) consisting of an envelope-tracking supply modulator (ETSM), a dual-power-mode power amplifier (PA), and a single-pole-double-throw (SPDT) switch is proposed for the Long-Term Evolution-Advanced (LTE-A) intraband carrier aggregation (CA) signal. The linear stage of ETSM is implemented by introducing the dual-path crossover current-reuse mechanism to obtain the measured efficiency 79.6%, 76.4%, 74%, and 72.8% for 7.4-, 9.6-, 11.2-, and 12.3-dB peak-to-average-power ratio (PAPR) 16-QAM LTE-A CA signals with $1 \times 20$ , $2 \times 20$ , $3 \times 20$ , and $4 \times 20$ MHz bandwidths, respectively. A SiGe BiCMOS dual-power-mode PA with two output power modes is realized and incorporated with ETSM to improve the adjacent channel leakage ratio (ACLR) by 11.7, 7.9, and 4.7 dB and the error vector magnitude (EVM) by 7.1%, 6.1%, and 4.1% at 26.8-, 24.3-, and 21.7-dBm output powers for the LTE-A 16-QAM signals with $1 \times 20$ , $2 \times 20$ , and $3 \times 20$ MHz bandwidths at 1.95 GHz, respectively. The SPDT switch integrated with ETSM provides 0.3-dB power loss reduction, 1.1-dB ACLR improvement, and 0.7% EVM enhancement at 12-dBm average input power. The ETFEM operated at 12.5-dB PAPR 64-QAM LTE-A CA signal with $4 \times 20$ MHz bandwidth demonstrates that the improvements of 1.3-dB ACLR and 1% EVM at 13.1-dBm output power are achieved for the wide-bandwidth and high-linearity FEM applications.

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  • ...GaAs pHEMT, silicon-on-sapphire, and silicon-oninsulator switches are widely used today since they offer an insulating substrate for stacking devices [26], [27]....

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Abstract: This article presents a dual-band millimeter-wave front end in 45-nm CMOS silicon-on-insulator (SOI) for 5G applications. The front end is composed of a low-noise amplifier (LNA), power amplifier (PA), and a single-pole double-throw (SPDT) switch. A double-tuned PA is used and is based on a two-stage stacked amplifier with a reconfigurable load using SOI switches, so as to achieve an optimal load for both 28- and 39-GHz 5G NR bands. A wideband series-shunt switch is also developed with high power handling (P1dB >22 dBm) and $P_{\mathrm {sat}}$ is > 18.8 dBm and the peak PAE is 18% at 24–30 GHz and includes the switch loss and compression. For high-band operation, the gain at 36–40 GHz is 13.6 ± 1.5 dB with $P_{\mathrm {sat}} > 18$ dBm. To the best of our knowledge, this is the first front end that covers both the 24–28- and 37–40-GHz 5G bands with high output power and low-NF. Application areas are in multistandard base stations and small cells.

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  • ...In order to achieve high linearity, the switch employs stacked transistors to divide the voltage swing across multiple transistors [19]–[21]....

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  • ...Therefore, for a wideband design, the series-shunt switch topology is still one of the best choices [19]–[23], provided that it is used with a minimal number of passive components for reduced loss, and the transistors are sized appropriately....

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  • ...In recent years, many microwave switches, which can select either the Tx or the Rx path for transmitter or receiver, respectively, have been designed by field-effect transistors or p-i-n diodes based on different process [5]–[8]....

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TL;DR: In this paper, an ultracompact monolithic millimeter-wave integrated circuit Doherty power amplifier (DPA) using a novel reconfigurable input network at Ka-band is presented.
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TL;DR: In this paper, the authors present the development of an ultra-wideband and 1-W voltage-controlled attenuator (VCA) using a 0.15-μm enhancement mode gallium arsenide pseudomorphic high-electron mobility transistor technology.
Abstract: We present the development of an ultra-wideband and 1-W voltage-controlled attenuator (VCA) using a 0.15- $\mu \text{m}$ enhancement mode gallium arsenide pseudomorphic high-electron mobility transistor technology. For the first time, a 2-D stacked field-effect transistor configuration is employed in a distributed VCA to simultaneously achieve wide bandwidth, high power, high dynamic range, and low insertion loss. The systematic design methodology is proposed, and a VCA prototype is fabricated and measured for verification. The monolithic microwave integrated circuit (MMIC) VCA exhibits a measured insertion loss of 1.9–5.5 dB from 1.5–45 GHz. The measured highest input 1-dB power compression point ( $P_{\mathrm {1dB}}$ ) is 30 dBm with a dynamic range of 26 dB. To the best of the authors’ knowledge, this paper reports the highest bandwidth and $P_{\mathrm {1dB}}$ of a single MMIC VCA while still maintaining excellent performance regarding dynamic range, insertion loss, and chip size.

16 citations


Cites methods from "A K-Band High Power and High Isolat..."

  • ...Stacked FETs were introduced in [24] and have been presented in different circuits: GaAs power amplifier [25], Doherty amplifier [26], Si CMOS amplifier [27], and transmit/ receive (T/R) switch [28]....

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References
More filters
Journal ArticleDOI
TL;DR: In this paper, the authors present designs and measurements of Ka-band single-pole single-throw (SPST) and singlepole double throw (SPDT) 0.13-CMOS switches.
Abstract: This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P1) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.

95 citations

Journal ArticleDOI
TL;DR: In this article, a novel ohmic electrode sharing technology (OEST) has been developed for MMIC switches with series-shunt FET configuration for millimeter-wave communications and radar systems.
Abstract: Compact DC-60-GHz heterojunction field-effect transistor (HJFET) monolithic-microwave integrated-circuit (MMIC) switches have been demonstrated for millimeter-wave communications and radar systems To reduce the MMIC chip size, a novel ohmic electrode-sharing technology (OEST) has been developed for MMIC switches with series-shunt FET configuration Four FET's of the series-shunt single-pole double-throw (SPDT) MMIC switch were integrated into an area of approximately 0018 mm/sup 2/ The developed MMIC switches have a high power-handling capability with low insertion loss (IL) and high isolation (Iso) at millimeter-wave frequencies From DC to 60 GHz, the single-pole single-throw (SPST) MMIC switch achieved the IL and Iso of better than 164 and 206 dB, respectively At 40 GHz, the IL increases by 1 dB at the input power of 21 dBm A novel large-signal FET model for the switch circuit is presented The simulated power-transfer performance shows the excellent agreement with the measured one The developed MMIC switches will contribute to the low-cost and high-performance millimeter-wave communications and radar systems

63 citations


"A K-Band High Power and High Isolat..." refers background or methods in this paper

  • ...In [4], authors used the ohmic-electrode-sharing technology for a Ka-band switch; however, the design gives only 20....

    [...]

  • ...in [4,6], the isolation of our approach is increased by at least 15 to 20 dB....

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Journal ArticleDOI
TL;DR: In this paper, a low-loss, inductive gate bias network structure for high-power RF switching applications is described, and the design, implementation, and performance of S and C-band SPDT switches based on this structure are described.
Abstract: A low-loss, inductive gate bias network structure which allows a very high stacking level of FET devices for high-power RF switching applications is reported. The design, implementation, and performance of S- and C-band SPDT switches based on this structure are described. Multiple GaAs MMIC chips integrated into a suspended-substrate hybrid circuit are used. At S-band, switch risetimes/falltimes of less than 40 ns and an RF power handling capability of 300 W CW have been demonstrated. This input signal level could be maintained during the switch state transitions (hot-switching), while being switched between the two output ports at rates of up to 500 kHz. >

49 citations


"A K-Band High Power and High Isolat..." refers background in this paper

  • ...A multiple stacked-FET switch was introduced in [2,7] to enhance output power at high frequency....

    [...]

01 Jan 1999
TL;DR: The operation of FETs as switches are described and design techniques for realising integrated RF and microwave switches are presented and consideration is also given to techniques for improving the power handling capability of switch designs.
Abstract: ∗ Liam Devlin is with Plextek Communications Technology Consultants, London Road, Great Chesterford, Essex, CB10 1NY Tel: +44 (0)1799 533200 Fax: +44 (0)1799 533201 Email: lmd@plextek.co.uk Integrated analogue switches can easily be designed using any Field Effect Transistor (FET) based process [1]. The challenges in switch design tend to come in extending the upper operating frequency and/or increasing the power handling capability. The first part of this paper describes the operation of FETs as switches and presents design techniques for realising integrated RF and microwave switches. Consideration is also given to techniques for improving the power handling capability of switch designs. Phase shifting circuits allow control of the insertion phase of a network. They find applications in electronic beam-forming, channel matching networks and measurement systems. The second part of this paper details phase shifting techniques suitable for integrated realisations. Analogue and digitally controlled techniques are included and examples of phase shifter designs are presented. Switch Design Introduction The FET’s suitability for switch realisation stems from the fact that its drain-source resistance behaves as a voltage variable resistor, the resistance being set by the gate-source voltage. When used as a switch, a FET is operated with the drain and source at zero volts DC. The RF signal path is drain to source and the gate is the control terminal. Figure 1 shows the typical I-V characteristics of a depletion mode FET about the Vds=0V point, for different (negative) Vgs bias voltages. It can be seen that, in the region of Vds=0V, the Vds/Ids characteristic approximates a resistance (Ids ∝ Vds). For Vgs=0V this is a low resistance (the FET is on) and for Vgs below pinch-off, the FET is off and presents a high resistance. This gives rise to the simple approximate equivalent circuit, shown in Figure 2. The gate resistor (Rg) is included as a simple and effective means of providing extra isolation between the signal and control path, a value of several kΩ is typically used. It is possible to use such a simple biasing technique because FETs draw very little gate current (typically < 0.5mA/mm for high gate-drain voltages and decreasing for lower). The very low DC power consumption of FET based switches is a significant advantage compared to PIN diode based switch designs. Figure 1: DC characteristics of a FET in the region of switch operation

44 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed a new design method for passive FET switches in the millimeter-wave (MMW) regime, which utilizes impedance transformation to compensate the drain-source capacitance effect for the off state at high frequencies.
Abstract: This paper proposes a new design method for passive FET switches in the millimeter-wave (MMW) regime. In contrast to the conventional resonant-type switch design method, this passive FET switch circuit utilizes impedance transformation to compensate the drain-source capacitance effect for the off state at high frequencies. By means of this new design concept, a Q- and V-band monolithic-microwave integrated-circuit single-pole double-throw (SPDT) switches using a GaAs pseudomorphic high electron-mobility-transistor process are demonstrated. The Q-band SPDT switch has a measured isolation better than 30 dB for the off state and 2-dB insertion loss for the on state from 38 to 45 GHz, while the V-band switch also shows a measured isolation better than 30 dB for the off state and 4-dB insertion loss for the on state from 53 to 61 GHz. The obtained isolation performance using this design approach outmatches previously published FET switches in the MMW frequency range.

43 citations


Additional excerpts

  • ...The impedance transformation switch was introduced in [5] to improve the isolation to 30 dB....

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Frequently Asked Questions (1)
Q1. What are the contributions mentioned in the paper "A k-band high power and high isolation stacked-fet single pole double throw mmic switch using resonating capacitor" ?

In this paper, a K-band single pole double throw ( SPDT ) switch with low insertion loss, high isolation and ultra high output power is demonstrated using 0.15-m Gallium Arsenide ( GaAs ) technology.