Proceedings ArticleDOI
A low-noise self-calibrating dynamic comparator for high-speed ADCs
Masaya Miyahara,Yusuke Asada,Daehwa Paik,Akira Matsuzawa +3 more
- pp 269-272
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TLDR
In this paper, a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique is presented, which does not require any amplifiers for the offset voltage cancellation and quiescent current.Abstract:
This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.read more
Citations
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Journal ArticleDOI
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
Lukas Kull,Thomas Toifl,Martin L. Schmatz,Pier Andrea Francese,Christian Menolfi,Matthias Braendli,Marcel Kossel,Thomas Morf,Toke Meyer Andersen,Yusuf Leblebici +9 more
TL;DR: An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ per conversion step.
Journal ArticleDOI
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
TL;DR: This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array, thereby decoupling comparator noise from ADC performance.
Journal ArticleDOI
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry
Kenichi Okada,Keitarou Kondou,Masaya Miyahara,Masashi Shinagawa,Hiroki Asada,Ryo Minami,T. Yamaguchi,Ahmed Eleojo Musa,Yuuki Tsukui,Yasuo Asakura,Shinya Tamonoki,Hiroyuki Yamagishi,Yasufumi Hino,Takashi Sato,Hironori Sakaguchi,N. Shimasaki,Toshihiko Ito,Yasuaki Takeuchi,Ning Li,Qinghong Bu,Rui Murakami,Keigo Bunsen,Kouta Matsushita,Makoto Noda,Akira Matsuzawa +24 more
TL;DR: This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions, capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60- GHz standards, which can be extended up to 10 Gb/s.
Journal ArticleDOI
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface
TL;DR: Detailed analysis proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages by effectively eliminating static power consumption in the proposed time-domain comparator.
Journal ArticleDOI
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
Yong Lim,Michael P. Flynn +1 more
TL;DR: A new fully differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of high gain, fast slew based charging and an almost rail-to-rail output swing is introduced.
References
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Book
Principles of Data Conversion System Design
TL;DR: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-toanalog conversion and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level.
Proceedings ArticleDOI
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Proceedings ArticleDOI
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process
TL;DR: A high-speed 4b flash ADC in 90nm digital CMOS is presented that uses a dynamic offset-compensation scheme in its comparators that achieves a sampling rate of 1.25GS/s with 3.7 ENOB (23.8dB SNDR) from dc to Nyquist while consuming 2.5mW.
Proceedings ArticleDOI
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS
TL;DR: SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range, but when the comparator determines in first instance the overall performance, comparator thermal noise can limit the maximum achievable resolution.