IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009 3253
A Low Noise Sub-Sampling PLL in Which Divider
Noise is Eliminated and PD/CP Noise is Not
Multiplied by
N
2
Xiang Gao, Student Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE,
Mounir Bohsali, Student Member, IEEE, and Bram Nauta, Fellow, IEEE
Abstract—This paper presents a 2.2-GHz low jitter sub-sam-
pling based PLL. It uses a phase-detector/charge-pump (PD/CP)
that sub-samples the VCO output with the reference clock. In
contrast to what happens in a classical PLL, the PD/CP noise is
not multiplied by
2
in this sub-sampling PLL, resulting in a
low noise contribution from the PD/CP. Moreover, no frequency
divider is needed in the locked state and hence divider noise
and power can be eliminated. An added frequency locked loop
guarantees correct frequency locking without degenerating jitter
performance when in lock. The PLL is implemented in a standard
0.18-
m CMOS process. It consumes 4.2 mA from a 1.8 V supply
and occupies an active area of 0.4
0.45 mm
2
. With a frequency
division ratio of 40, the in-band phase noise at 200 kHz offset
is measured to be
126 dBc/Hz. The rms PLL output jitter
integrated from 10 kHz to 40 MHz is 0.15 ps.
Index Terms—Clock generation, clock multiplier, clocks, fre-
quency multiplication, frequency synthesizer, jitter, loop noise,
low jitter, low phase noise, low power, phase detector, phase locked
loop (PLL), phase noise, sampling phase detector, sub-sampling
phase detector, timing jitter.
I. INTRODUCTION
A
STABLE clock with low jitter and phase noise is a
prerequisite for a variety of applications like high per-
formance analog-to-digital converters, wireline and optical
serial data communication links and radio transceivers. Of the
many known PLL architectures [1], [2], the most widely-used
“classical PLL” architecture [3]–[9] has a frequency divider
divide-by-
, a phase-detector(PD)/charge-pump(CP), a loop
filter (LF) and a voltage controlled oscillator (VCO), see
Fig. 1(a). A linear, phase domain model for the classical PLL
together with various noise sources is shown in Fig. 1(b), with
the PD/CP detection gain, the LF (trans-)impedance
transfer function and
the VCO tuning gain. The PLL
phase noise can be divided into two parts: 1) the VCO (and LF)
noise which dominates out-of-band; 2) the loop noise (noise
from the reference clock, PD/CP and divider) which dominates
in-band as illustrated in Fig. 1(c). In an optimized PLL, the
two types of noise contribute equally to the output jitter [2],
Manuscript received April 17, 2009; revised August 03, 2009. Current version
published December 11, 2009. This paper was approved by Guest Editor Vadim
Gutnik.
X. Gao, E. A. M. Klumperink, and B. Nauta are with the IC-Design
group, University of Twente, 7500 AE Enschede, The Netherlands (e-mail:
x.gao@utwente.nl).
M. Bohsali is with National Semiconductor, Santa Clara, CA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2009.2032723
Fig. 1. Classical PLL (a) architecture, (b) phase domain model, (c) phase noise
spectrum (
1
=f
noise neglected).
[10] and thus are equally important. The VCO phase noise has
been studied in literature and noise reduction techniques have
been addressed, e.g., in [11]–[13]. The focus of this paper is
on reducing the loop noise, i.e., the PLL in-band phase noise.
In a classical PLL, the main loop noise sources are usually the
PD/CP and the divider. Due to the existence of the divide-by-
in the feedback path, the PD/CP and divider noise (in power) is
multiplied by
when transferred to the PLL output.
Unlike the classical phase detectors, e.g., the well-known
three-state phase frequency detector (PFD), a sampling or
sample-and-hold PD [1], [14] can work without using a divider.
Thus, divider noise and power dissipation can be eliminated.
However, using a sampling PD has drawbacks like the need for
a large filter capacitor due to its large detection gain and limited
acquisition range [1], which have kept it from wide use in
fully integrated PLLs. In this paper, we describe our proposed
(sub-)sampling PLL architecture [16] which overcomes the
aforementioned drawbacks. In addition to the elimination of
divider noise, analysis shows that, in contrast to what happens
in a classical PLL, the PD/CP noise is not multiplied by
in this PLL. As a result, the in-band phase noise is greatly
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3254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009
improved which leads to a PLL design with very low jitter as
well as low power.
This paper is arranged as follows. Section II discusses
and compares the CP noise contributions in a PLL using a
classical three-state PFD/CP and a PLL using a sub-sampling
PD/CP. Section III describes the complete sub-sampling PLL
architecture and the design techniques used to overcome the
sub-sampling PLL drawbacks. The circuit level design is de-
scribed in Section IV and the experimental results are presented
in Section V. Finally, Section VI draws conclusions.
II. L
OW
NOISE PHASE
DETECTION
In the following sections, we will discuss the PD/CP noise,
with focus on the CP noise which often dominates. In order to
calculate the CP noise contribution in a feedback system like
a PLL, it is convenient to define a CP feedback gain
as
the gain from the PLL output to the CP output current. Using
the phase domain model in Fig. 1(b), the close loop CP noise
transfer function can be calculated as
(1)
where
is the PLL open loop transfer function.
Inside the PLL bandwidth,
and the PLL in-band
phase noise contributed by the CP can be approximated as
(2)
where the phase noise is expressed with the often used single
sideband noise power to carrier power ratio
and is the
power spectral density of the CP current noise.
Equation (2) indicates that the CP noise is suppressed by
when transferred to the PLL output. A larger is
thus desired as it provides more suppression for the CP noise.
A. Classical Three-State PFD/CP
For PLL designs, the three-state PFD/CP as shown in Fig. 2
is often used. The VCO output is firstly divided down so that the
divider output Div has the same frequency as the reference clock
Ref. The timing/phase of Div and Ref are then compared and
the CP outputs a current pulse with width equal to the amount
of timing/phase error. The CP feedback gain of the classical
three-state PFD/CP can be calculated as
(3)
where
is the bias current of the CP current sources,
is the mean CP output current, and are respec-
tively the VCO and divider phase error.Equation (3) indicates
that
is reduced by the frequency division ratio . That
is the reason why the CP noise power is multiplied by
as ac-
cording to (2) the CP noise contribution is inversely proportional
to
.
The reduction of
by the division ratio is perhaps
easier understood in the time domain where the VCO timing
error is directly transferred to the divider output without scaling.
When a timing error
between the VCO/Div and Ref is de-
tected, the CP will output a current pulse with width
. The
mean CP output current is then
with the pe-
riod of Ref. If we increase
while keeping the same,
becomes lower and becomes larger. On the other hand,
the width of the CP output current pulse remains the same for
the same amount of VCO/Div timing error. Consequently, the
mean CP output current becomes smaller due to the larger
,
corresponding to a lower
.
It is possible to physically eliminate the divider (and its noise
contribution) and design a three-state PFD/CP based divider-
less PLL as proposed in [17], where the PFD compares the
phase of the VCO and Ref at every rising edge of Ref for only
a small time window (aperture). However, since the phase de-
tection mechanism remains the same,
remains propor-
tional to
meaning that it is still reduced by and the
CP noise is still multiplied by
.
In steady state, a CP driven by a PFD is switched on only
for
in each period . Assuming that the noise of the
CP UP/DN current source is dominated by a single MOS tran-
sistor with transconductance
, the power spectral density of
the (thermal) noise generated by the CP can be estimated as [10]:
(4)
where
is a noise model parameter of the MOS transistor typ-
ically in the range of 2/3 to 1.5.
B. Proposed Sub-Sampling PD/CP
The sampling based PD has been known for years [14]. Fig. 3
shows its conceptual diagram and timing diagram. The VCO
output, a sine wave with amplitude
and DC voltage ,
is sampled by a reference clock Ref. When the VCO and Ref
are phase aligned and their frequency ratio
is an integer, the
sampled voltage
has a constant value equal to . When
there is phase error between the VCO and Ref,
will de-
viate from
. The voltage difference between and
represents the amount of phase error as shown in Fig. 3(b). Note
that this PD works without using a divider as soon as the ratio
is an integer, which is an often mentioned reason to
use it. However, we will show below that a (sub-)sampling PD
can also bring a significant phase noise benefit.
In a sampling PD, the timing/phase error is converted into
voltage error. Since the high frequency VCO has a high slew
rate:
, a high detection gain can be
expected. Fig. 4(a) shows the first step toward our sub-sampling
PD/CP (SSPD/CP) proposal. The name sub-sampling is used to
stress that the high frequency VCO is sampled by a low fre-
quency Ref. In order to process
via the traditional current
driven loop-filter, a transconductor converts voltage
into
current
, acting as UP current source. The DN current
source is controlled by
, the expected VCO voltage when
sampled at the crossing moment. Thus, in contrast to a tradi-
tional CP, the output current is not proportional to
,but
rather amplitude controlled by the difference of
and ,
which is proportional to
. The transfer characteristic
of the SSPD/CP has the same shape as the VCO waveform, as
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GAO et al.: A LOW NOISE SUB-SAMPLING PLL IN WHICH DIVIDER NOISE IS ELIMINATED AND PD/CP NOISE IS NOT MULTIPLIED BY 3255
Fig. 2. Three-state PFD/CP: (a) schematic, (b) timing diagram, (c) characteristic.
Fig. 3. Sampling based PD: (a) conceptual diagram; (b) timing diagram.
shown in Fig. 4(b). The ideal locking point is the crossing mo-
ment of the sine wave (corresponding to
) where it
is most linear. The sinusoidal characteristic of the SSPD is sim-
ilar to that of a mixer based phase detector. However, the SSPD
is not sensitive to the duty cycle or shape of the sampling ref-
erence clock as it only takes one sample per period instead of
processing the whole VCO waveform.
The architecture of a PLL utilizing the SSPD/CP, which we
call a sub-sampling PLL (SSPLL), is shown in Fig. 5(a). In the
steady state, the VCO phase error is small and the CP feedback
gain of the SSPLL can be calculated as
(5)
We see that there is no
in (5), which means that is
not related to
. Consequently, the CP noise of the SSPLL is
not multiplied by
when transferred to the output.
Assuming that the CP current source is implemented with a
single square-law MOS transistor, (5) can be rewritten as
(6)
where
is the effective gate-source voltage of the MOS
transistor and
represents .
Unlike the three-state PFD/CP, the two current sources in the
SSPD/CP are always on. The equivalent CP (thermal) noise cur-
rent can be estimated as
(7)
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3256 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 12, DECEMBER 2009
Fig. 4. Conceptual schematic and characteristic of a sub-sampling based PD/CP.
Fig. 5. Sub-sampling PLL: (a) architecture, (b) phase domain model.
C. CP Noise Comparison
In this section, we compare the CP noise contribution of a
classical PLL using the three-state PFD/CP and a SSPLL using
the SSPD/CP. In both PLLs, the CP noise contribution can be
reduced by increasing the CP bias current
. For a fair com-
parison, we assume the two CPs use equal
.
The CP feedback gain of the classical PLL and the SSPLL
can be compared using (3) and (6) as
(8)
It is easy to see that (8) is much larger than 1 as
,
and usually . Thus,
the SSPLL has a much larger
than the classical PLL, and
thus has much more suppression for the CP noise.
On the other hand, the CP in the SSPLL is always on and
continuously injects noise to the loop filter, while the CP in
the classical PLL only injects noise for a fraction of time
during each . Effectively, the CP in the classical PLL gen-
erates
times less (thermal) noise than the CP in the
SSPLL:
(9)
Overall, the in-band phase noise due to the CP of the two
PLLs can be compared using (2), (8) and (9) as
(10)
Fig. 6. Theoretical CP noise improvement factor (10) as a function of the
VCO frequency for various reference frequencies, assuming
A
=0
:
4
V,
V
=0
:
2
V and
= 200
ps.
The value of (10) indicates the amount of CP noise reduction
we can achieve by using a SSPLL instead of a classical PLL.
Assuming
, and ps,
the ratio in (10) is plotted in Fig. 6 for
ranging from 1 MHz
to 100 MHz and
ranging from 100 MHz to 10 GHz. We
see that the SSPLL has orders of magnitude less CP contributed
in-band phase noise than the classical PLL. The advantage of the
SSPLL is larger when a higher
or a lower are used.
III. S
UB-SAMPLING PLL
Although the sampling PD has been existing for years, its po-
tential of achieving very low in-band phase noise is not fully
appreciated to the best of our knowledge. It also has drawbacks
like difficulty of integration (large filter capacitor needed) and
limited frequency acquisition range [1], which have kept it from
wide use in full integrated PLLs. The sampling PD has been
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GAO et al.: A LOW NOISE SUB-SAMPLING PLL IN WHICH DIVIDER NOISE IS ELIMINATED AND PD/CP NOISE IS NOT MULTIPLIED BY 3257
used in a MMIC PLL [15] and a DLL [22]. However, both of
them use off-chip loop filters. The CDR in [21] also uses a sam-
pling PD but the division ratio is one. To the best of the authors’
knowledge, our design [16] is the first fully integrated sub-sam-
pling PD based PLL. In the following sub-sections, we will build
a phase domain model for the SSPLL and compare its phase
noise with the classical PLL. We will also discuss SSPLL draw-
backs and propose design techniques [16] to overcome them.
A. Modeling and Noise Analysis
A linear phase-domain model for the SSPLL is shown in
Fig. 5(b). Here we model the SSPLL as a time continuous
system, which is valid as soon as the PLL bandwidth is an order
of magnitude smaller than
[18]. In case the bandwidth
is higher, the sampling effects will affect loop stability. They
can be modeled using the method in [1] and can be added into
Fig. 5(b).
Unlike the classical PLL, there is no divide-by-
in the feed-
back path in the SSPLL model. Instead, a virtual frequency mul-
tiplier “
” is added to the reference clock path. This (physi-
cally non-existing) multiplier originates from the sub-sampling
process. When the high frequency VCO is sub-sampled by the
low frequency Ref, the baseband alias falling in the loop filter
band has a frequency of:
(11)
Therefore, the sub-sampling process works as if the VCO is
sampled by a signal with frequency
times higher than Ref.
In other words, the frequency and thus phase of Ref is virtually
multiplied by
. Viewed in another way, the sampler output
voltage is proportional to the timing error between the VCO
and Ref. However, a given timing error corresponds to
times
more phase error if we refer it to the VCO instead of Ref since
. As the phase of the VCO is subtracted at the
phase comparison point, a multiplication
of the phase of
Ref before this subtraction point is incorporated in the model.
Using this phase domain model for noise analysis, we see that
the reference clock phase noise is still multiplied by
when
transferred to the output, same as in a classical PLL. However,
due to the absence of the divide-by-
in the feedback path
1
both
the CP and PD noise is not multiplied by
. Moreover, the
SSPLL does not need a divider in the locked state, thus the di-
vider noise is eliminated. Therefore, we can expect the SSPLL
to achieve a much lower in-band phase noise than the classical
PLL. The CP noise analysis was already done in Section II
(Fig. 6). The noise contribution of the SSPD can be calculated
by relating the voltage noise at the SSPD output
and
the corresponding VCO phase error in steady state:
(12)
where
is the sampling capacitor value.
Assuming white noise and using the fact that the SSPD noise
is band-limited by
due to sampling, the PLL in-band
phase noise due to the SSPD can be calculated as
(13)
1
Compared with the divider-less PLL in [17], the SSPLL does not only elim-
inate the physical divider, but also eliminate the divider in the phase domain
model. In this sense it is a truly divider-less PLL.
Using (12) and (13), we get:
(14)
We see that the SSPD noise is indeed not multiplied by
.
Because of that, its contribution to the overall in-band phase
noise can be small without using a big
. As a numerical ex-
ample, with
MHz and ,a is
sufficient to bring
to be as low as 133 dBc/Hz.
B. Chip Area Considerations
In a charge pump PLL, the most common implementation of
the loop filter is a passive RC filter where a resistor
is in
series with a capacitor
. A second capacitor is often added
in parallel to reduce the voltage ripple. In order to integrate the
loop filter on chip, the value of
and should not be too
large. In the following discussions we will neglect
since it is
much smaller than
and is not the major concern.
Substituting the loop filter transfer function
into the PLL phase domain model in Fig. 5(b), the PLL
open loop bandwidth
and the frequency of the loop gain zero
can be expressed as
(15)
(16)
Combining (15) and (16), we get:
(17)
In (17),
is related to the VCO analog tuning range re-
quirement and
is related to the phase margin require-
ment. Once they are specified, the bracketed part is a constant.
The value of
is thus proportional to and inversely pro-
portional to the square of
.
In order to achieve low output jitter, the PLL bandwidth
needs to be carefully chosen. The optimal bandwidth for
minimum jitter is roughly where the spectrum of the VCO and
the loop noise intersects [2], [10]. For lower loop noise,
is thus higher, requiring a smaller . When the loop noise is
dominated by the CP noise, having a larger
reduces the loop
noise and increases
as shown in Fig. 7(a). However, when
the CP noise becomes negligible and other loop components’
noise start dominating the loop noise, having a further larger
still reduces the CP noise but will hardly reduce the overall
loop noise as shown in Fig. 7(b). In the latter case, increasing
further can not increase , but does require a larger
to stabilize the PLL. Such an “unnecessarily high” will
thus make full integration difficult. Fig. 6 shows that the SSPLL
reduces the CP noise contribution so much that it easily becomes
negligible. Therefore,
easily enters the “unnecessarily
high” region and it is actually desired to reduce
in order
to reduce filter capacitor area.
C. SSPD/CP With Gain Control
Fig. 8 shows the proposed SSPD/CP with gain reduction. In-
stead of leaving the CP always on, two switches and a block
called “Pulser” are added. Also, antiphase VCO outputs and
differential sampling are used. The locking point is then the
crossing moment of the differential VCO outputs with no need
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