Journal ArticleDOI
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
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A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS)chip multiprocessors that eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates.Abstract:
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates. In particular, two new highly-concurrent asynchronous components are introduced which provide simple routing and arbitration/merge functions. Post-layout simulations in identical commercial 90 nm technology indicate that comparable recent synchronous router nodes have 5.6-10.7 more energy per packet and 2.8-6.4 greater area than the new asynchronous nodes. Under random traffic, the network provides significantly lower latency and identical throughput over the entire operating range of the 800 MHz network and through mid-range traffic rates for the 1.36 GHz network, but with degradation at higher traffic rates. Preliminary evaluations are also presented for a mixed-timing (GALS) network in a shared-memory parallel architecture, running both random traffic and parallel benchmark kernels, as well as directions for further improvement.read more
Citations
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Globally-Ratiochronous, Locally-Synchronous Systems
TL;DR: This work proposes Globally-Ratiochronous, Locally-Synchronous (GRLS) systems, where GRLS is a design style intermediate between the mesochronous and the GALS design paradigms: local frequencies in a GRLS system do not need to be identical, but are required to be rationally-related, which results in high figures of merit for GRLS systems.
Journal ArticleDOI
High-Performance Asynchronous Pipelines: An Overview
Steven M. Nowick,Montek Singh +1 more
TL;DR: This tutorial provides an overview of the best-in-class asynchronous pipelining methods that can be used to fully exploit the advantages of this design style, covering both static and dynamic logic implementations.
Proceedings ArticleDOI
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems
TL;DR: A largely unexplored design point for asynchronous NoCs, relying on transition-signaling bundled data, which contributes to break the above barriers is proposed, and an existing lightweight synchronous switch architecture, xpipesLite is compared.
Proceedings ArticleDOI
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools
TL;DR: This tutorial will cover the basic principles and advantages of asynchronous logic, some insights on new research challenges, and will present the GALS scheme as an intermediate design style with recent results in asynchronous Network-on-Chip for future Many Core architectures.
Proceedings ArticleDOI
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
TL;DR: A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors that eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates.
References
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Networks on chips: a new SoC paradigm
Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Book
Principles and Practices of Interconnection Networks
William J. Dally,Brian Towles +1 more
TL;DR: This book offers a detailed and comprehensive presentation of the basic principles of interconnection network design, clearly illustrating them with numerous examples, chapter exercises, and case studies, allowing a designer to see all the steps of the process from abstract design to concrete implementation.
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Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes
TL;DR: This chapter discusses sorting on a Linear Array with a Systolic and Semisystolic Model of Computation, which automates the very labor-intensive and therefore time-heavy and expensive process of manually sorting arrays.
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Digital integrated circuits: a design perspective
TL;DR: In this paper, the authors present a survey of the state-of-the-art in the field of digital integrated circuits, focusing on the following: 1. A Historical Perspective. 2. A CIRCUIT PERSPECTIVE.
Journal ArticleDOI
The Torus Routing Chip
TL;DR: The torus routing chip (TRC) is a selftimed chip that performs deadlock-free cut-through routing ink-aryn-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels.