A Low Power 10 bit 50-MS/s Sample and Hold OTA Amplifier
24 Feb 2018-pp 33-37
TL;DR: An Improved Recycling Folded Cascade (IRFC) OTA existing in the literature is used for realizing SHA and is proposed and achieves a DC gain of 73 dB, Unity Gain Bandwidth (UGB) of 70 MHz and with a phase margin of 63 degrees.
Abstract: This paper presents about the design of a low power 10-bit 50-M sample /sec Sample and Hold amplifier. A sample and hold amplifier (SHA) acts as a front end block for an Analog Digital Circuit (ADC). To realize a low power SHA, a power efficient Operational Tran-conductance Amplifier (OTA) is to be designed and used. In the literature, many topologies of OTA are proposed for low power. In this paper, an Improved Recycling Folded Cascade (IRFC) OTA existing in the literature is used for realizing SHA and is proposed. In addition to this the SHA includes bottom plate sampling and bootstrap switch to reduce the non-linear distortion. The IRFC OTA used in the design of SHA is implemented using TSMC 90 nm Process. It achieves a DC gain of 73 dB, Unity Gain Bandwidth (UGB) of 70 MHz and with a phase margin of 63 degrees. The proposed SHA is designed and simulated using spectre simulator. From the simulation, it is noted that the SHA achieves a Spurious Free Dynamic Range (SFDR) of 63.44dB and SNDR of 60.6dB for a sampling frequency of 50MS/s with a peak-peak voltage of 1.2 Volts. The S/H circuit consumes 0.44mW of power.
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01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.
1,038 citations
TL;DR: A re-configurable pipeline analog-to-digital converter (ADC) deliberated for implantable surveillance devices for bio-impedance monitoring systems and an automatic adaptation circuit is introduced to improve the efficiency of the bio-IMpedance method.
Abstract: This article introduces a re-configurable pipeline analog-to-digital converter (ADC) deliberated for implantable surveillance devices for bio-impedance monitoring systems. To improve the efficiency of the bio-impedance method, an automatic adaptation circuit is introduced. This adaptive unit is responsible for setting the resolution and sampling rate on the basis of amplitude and frequency of the signal. Using a new, low-power automatic adaptation circuit low power consumption is achieved by using Dynamic Threshold metal oxide semiconductor (DTMOS) technique, it can automatically determine its setup. The converter has two modes of operations. In high-resolution mode, the converter has a 12-bit resolution and at low resolution mode, 8-bit resolution is used. The ADC bandwidth of low-speed mode is 100 kHz and high-speed mode is 1 GHz. The architecture is designed using 180 nm technology and simulated using Cadence virtuoso tool. The results achieved, low power consumption i.e. 0.844 mw, and it is operated with 1 V power supply. For signal to noise and distortion ratio (SNDR), effective number of bits (ENOB), the converter utilizes 71.06 dB, 11.45 in 12-bit and 72.3 dB, 7.41 in 8-bit mode respectively. By using proposed method around 20% of power consumption is reduced and 40% power supply is decreased. The proposed design is also used for mixed signal circuit testing.
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References
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Book•
01 Jan 1999
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents
1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging
4,826 citations
01 Jan 2016
TL;DR: The design of analog cmos integrated circuits is universally compatible with any devices to read and is available in the book collection an online access to it is set as public so you can download it instantly.
Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.
1,038 citations
"A Low Power 10 bit 50-MS/s Sample a..." refers background in this paper
...Out of this ADCs Pipeline ADC is chosen because of its performance with respect to power, area and sampling rate [1]....
[...]
...It is one of the blocks that consume more power [1] [4][9]....
[...]
TL;DR: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology.
Abstract: A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.
432 citations
TL;DR: A recycling amplifier architecture based on the folded cascode transconductance amplifier is described, which delivers an appreciably enhanced performance over that of the conventional folded by using previously idle devices in the signal path, which results in an enhanced transc conductance, gain, and slew rate.
Abstract: A recycling amplifier architecture based on the folded cascode transconductance amplifier is described. The proposed amplifier delivers an appreciably enhanced performance over that of the conventional folded. This is achieved by using previously idle devices in the signal path, which results in an enhanced transconductance, gain, and slew rate. Moreover, the input referred noise and offset analyses are included to demonstrate that the proposed modifications have no adverse effects on these design metrics. Transistor-level simulations and experimental results in TSMC 0.18 mum CMOS process confirm the theoretical results. When compared to the conventional folded cascode, and for the same area and power budgets, the proposed amplifier has almost twice the bandwidth (134.2 MHz versus 70.7 MHz) and better than twice the slew rate (94.1 V/mus versus 42.1 V/mus) while driving the same 5.6 pF load. Also a gain enhancement of 7.6 dB is observed.
333 citations
"A Low Power 10 bit 50-MS/s Sample a..." refers background in this paper
...So in the RFC [3] OTA as shown in the figure....
[...]
...Improved recycling folded cascade (IFRC) OTA [3] consumes low power and gives high gain when compared to other topologies in the literatures....
[...]
TL;DR: An enhanced fully differential folded-cascode operational-amplifier topology that achieves improved DC gain and common-mode rejection without sacrificing slew rate is presented and is verified by simulations and preliminary experimental results.
Abstract: An enhanced fully differential folded-cascode operational-amplifier topology that achieves improved DC gain and common-mode rejection without sacrificing slew rate is presented. The large-signal operation of the new topology is completely symmetric, providing equal positive and negative slew-rate behavior by making use of current mirrors rather than current sources as normally found in full differential folded-cascode op-amps. An additional advantage of the enhanced topology is that its common-mode output impedance is a factor of g/sub m/r/sub o/ (typically 1-2 orders of magnitude) lower than the differential-mode output impedance, significantly improving the common-mode rejection ratio. The predicted performance is verified by simulations and preliminary experimental results. >
66 citations