A low-power 2-GSample/s comparator in 120 nm CMOS technology
05 Dec 2005-pp 507-510
TL;DR: A delayed reset signal is used to enhance the output voltage difference with the help of charge injection and the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution.
Abstract: This paper presents a comparator in 120nm digital CMOS technology with a supply voltage of 1.5V. In contrast to common comparator structures a delayed reset signal is used to enhance the output voltage difference with the help of charge injection. Furthermore the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution. For characterization several BER (bit-error-rate) measurements on the comparator have been made. For a BER of 109 the comparator is able to detect an input voltage difference of 9.5mV at a clock frequency of 1.5GHz and 16mV at 2.0GHz. The maximum power consumption of the comparator with two following additional transfer stages is 360/spl mu/W at 2.0GHz.
Citations
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29 Nov 2007
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as mentioned in this paper.
Abstract: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a one-sigma offset of 8mV, the circuit consumes 92fJ/decision at 1.2V supply. It has an input equivalent noise of 1.5mV and requires only 18ps setup plus hold time.
48 citations
01 Sep 2006
TL;DR: In this paper, a comparator with the capability of high decision speed, but static power consumption was avoided, and the circuit implements a technique to enhance resolution while keeping the ability of a high switching speed.
Abstract: This paper presents a comparator with the capability of a high decision speed, but static power consumption was avoided. Furthermore the circuit implements a technique to enhance resolution while keeping the ability of a high switching speed. During the reset phase the comparator is pulled to ground level, which defines a logic voltage level. A test chip with the comparator was manufactured in a 120nm CMOS technology with a supply-voltage of 1.5V. For a bit-error-rate (BER) of 10-9 the presented comparator is able to detect 11.2mV at 2GHz, 20mV at 3GHz, 26mV at 3.5GHz and 118mV at 4GHz. The power consumption was 788muW at 3.5GHz and 812muW at 4GHz
11 citations
Cites background from "A low-power 2-GSample/s comparator ..."
...In ADCs typically additional circuitry to the latch [2] [3] and pre-amplifiers, which enhance the resolution and reduce in some cases the overall offset, are added [4]....
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12 Nov 2007
TL;DR: An integrated 2-PPM CMOS demodulator for non-coherent energy detection receivers which inherently provides analog-to-digital conversion and its application is appealing for portable devices which aim at very low-power consumptions.
Abstract: This paper presents an integrated 2-PPM CMOS demodulator for non-coherent energy detection receivers which inherently provides analog-to-digital conversion. The device, called Bi-phase integrator, employs an open loop Gm - C integrator loaded with a switched capacitor network. The circuit has been simulated in a mixed-mode UMC 0.18mum technology and its performance figures are obtained through a mixed-signal simulation environment developed with the aid of ADVanceMS (ADMS, mentor graphics). Bit-error-rate simulations show that the circuit performance is about the same of an ideal energy detection receiver employing infinite quantization resolution. In addition, the simulations show that the circuit provides a complete offset rejection. Thanks to its low power consumption (lmW during demodulation), its application is appealing for portable devices which aim at very low-power consumptions.
5 citations
Cites background from "A low-power 2-GSample/s comparator ..."
...[2], [3] and lowpiower CMOS front-ends implementaton of In addition, the simulations show that the circuit provides a ED receivers are increasing during years [4]....
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22 Jun 2006
TL;DR: In this article, an on-chip measurement technique is presented to obtain the delay time of a regenerative comparator, where after sampling the logic decision at the inverted and non-inverted output of the comparator both outputs overlap with the same logical value.
Abstract: The delay time of a regenerative comparator can be in the range of some tens of picoseconds. In this paper, an on-chip measurement technique is presented to obtain this delay time. For this task simple RC low-passes and different variants of implementing a fast XOR gate are examined to determine a short time difference, where after sampling the logic decision at the inverted and non-inverted output of the comparator, both outputs overlap with the same logical value. This time-difference is identified as the delay time of the comparator and occurs, if in the reset phase of the comparator the output nodes are pulled to the same logical value. An advantage of this technique is that only a DC voltage has to be measured outside the chip, which is proportional to the delay time and which is not influenced by bond wire inductances. A test-chip with the low-power comparator and a test-bed for delay-time detection was manufactured in a 120nm CMOS technology with a supply voltage of 1.5V. Compared with simulation results it turns out that a simple RC low-pass is sufficient for delay measurements. When applying a rectangular signal at the input of the implemented comparator, a minimal resolution of 8mV at a clock frequency of 1.5GHz was reached. The power consumption of the comparator was 160muW at 1.5GHz and the offset voltage was typically l0mV
3 citations
Cites background from "A low-power 2-GSample/s comparator ..."
...In [3], [4] and [5] comparators for the use in an analog-to-digital converter (ADC) are described....
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...Compared to [3], where the power consumption was 350μW at 2GHz, a considerable saving of power is present, because there two transfer stages instead of two simple inverters are added to the latch....
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TL;DR: In this paper, a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm delta sigma modulator (DSM) utilizing a fully balanced active inductor was proposed.
Abstract: This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm2.
2 citations
Cites methods from "A low-power 2-GSample/s comparator ..."
...Hence, a low-power high-speed dynamic comparator presented in [ 30 ] is adopted our design, which consumes only 360 lW at 2 GHz and is shown in Fig. 16....
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...Fig. 16 Low power high speed dynamic comparator in [ 30 ]...
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References
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TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Abstract: A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.
450 citations
"A low-power 2-GSample/s comparator ..." refers background or methods in this paper
...The expression of [5] adapted for Fig....
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...A further example of an application is the use of a latch-type circuit as a voltage sense amplifier in a SRAM [5]....
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...1) with the complementary structure compared to that presented in [5]....
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...Therefore the rate of false decisions of the comparator can be reduced, if the input-common-mode level is risen, because the sum of the time for charging the output nodes and the following switching time of the latch keeps constant for a distinct range [5]....
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...In [5] an analytical expression for the A...
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TL;DR: It is shown first, theoretically as well as experimentally, that the average rate of system failures, due to the occurrence of metastable states (MSSs), is independent of circuit noise.
Abstract: Deals with the behavior of flip-flops, used as input synchronizers, in particular when they operate in the metastable region. It is shown first, theoretically as well as experimentally, that the average rate of system failures, due to the occurrence of metastable states (MSSs), is independent of circuit noise. A formula which describes the probability of occurrence of a metastable state has been derived. To verify the theory, measurements have been made on a flip-flop made in n-channel MOS technology. Also a method is given for predicting the average number of system failures, for a given flip-flop, occurring over a year. This method is applied to predict this average failure rate for the designed synchronizer.
249 citations
TL;DR: The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented and an extensive description of the implemented digital error correction technique is described.
Abstract: The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm/sup 2/. The ADC is implemented in a 0.25-/spl mu/m pure digital CMOS technology.
166 citations
"A low-power 2-GSample/s comparator ..." refers background in this paper
...When the output voltage difference is not large enough, so that the following logical gates may interpret a wrong logical value, this can be seen as metastability error [1], [3]....
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...In [3] and [4] comparators for use in analog-to-digital converters (ADC) are described....
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TL;DR: In this article, an offset compensation technique that can simultaneously minimize input-referred supply noise was proposed to reduce the resolution of a comparator by the dc input offset and the ac noise.
Abstract: The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.
116 citations
"A low-power 2-GSample/s comparator ..." refers background in this paper
...18μm technology in [6] a comparator needs 350μW at 1....
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07 Aug 2002
TL;DR: Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed.
Abstract: Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.
104 citations
"A low-power 2-GSample/s comparator ..." refers background in this paper
...In [3] and [4] comparators for use in analog-to-digital converters (ADC) are described....
[...]