A low-power 22-bit incremental ADC
TL;DR: A low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process, incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on- chip sinc filter.
Abstract: This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-mum CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 muVRMS), the DC offset 2 muV, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 muA current during conversion
Citations
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TL;DR: A CMOS-based microelectrode array system for in vitro applications that integrates six measurement and stimulation functions, the largest number to date, and features the largest active electrode array area to date.
Abstract: Biological cells are characterized by highly complex phenomena and processes that are, to a great extent, interdependent. To gain detailed insights, devices designed to study cellular phenomena need to enable tracking and manipulation of multiple cell parameters in parallel; they have to provide high signal quality and high-spatiotemporal resolution. To this end, we have developed a CMOS-based microelectrode array system for in vitro applications that integrates six measurement and stimulation functions, the largest number to date. Moreover, the system features the largest active electrode array area to date ( $4.48 \times 2.43$ mm2) to accommodate 59 760 electrodes, while its power consumption, noise characteristics, and spatial resolution (13.5- $\mu$ m electrode pitch) are comparable to the best state-of-the-art devices. The system includes: 2048 action potential (AP, bandwidth: 300 Hz–10 kHz) recording units, 32 local-field-potential (LFP, bandwidth: 1 Hz–300 Hz) recording units, 32 current recording units, 32 impedance measurement units, and 28 neurotransmitter detection units, in addition to the 16 dual-mode voltage-only or current/voltage-controlled stimulation units. The electrode array architecture is based on a switch matrix, which allows for connecting any measurement/stimulation unit to any electrode in the array and for performing different measurement/stimulation functions in parallel.
160 citations
Additional excerpts
...while relaxing the slewing requirements of the integrators, cascade-of-integrators with feed-forward (CIFF) topology was employed [44]....
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TL;DR: A 20-bit incremental ADC for battery-powered sensor applications is presented, based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion.
Abstract: A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2 chip was fabricated in a standard 0.16 μm CMOS process.
154 citations
Cites background or methods from "A low-power 22-bit incremental ADC"
...This eliminates the need for either state-preserving choppers around integrators [16] or complex sequencing of chopper control [2], which could be a potential source of charge injection....
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...In contrast to [2], [16], [20], this was implemented in a digital rather than an analog manner....
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...In Table I, the ADC’s performance is summarized and compared to other state-of-the-art in high resolution incremental ADCs [2], [3], [12], [14]....
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...Higher order or multi-bit architectures are faster, but reported implementations still only achieve moderate energy efficiency [2], [11], [12]....
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...(b) 1-bit 3rd order incremental ADC [2]....
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TL;DR: A calibration-free, high-resolution analog-to-digital converter designed for a bioluminescence sensor array employs incremental sigma-delta (ΣΔ) modulation to combine the advantages of oversampling with an input multiplexing capability.
Abstract: A calibration-free, high-resolution analog-to-digital converter designed for a bioluminescence sensor array employs incremental sigma-delta (ΣΔ) modulation to combine the advantages of oversampling with an input multiplexing capability. The resolution of incremental ΣΔ modulators can be improved significantly by means of a technique similar to extended counting. In the approach proposed in this paper, analog-to-digital conversion is accomplished with a two-step process in which the residual error from a second-order incremental ΣΔ modulator is encoded using a successive approximation ADC. By this means it is possible to achieve enhanced resolution and improved static linearity while maintaining a one-to-one mapping between individual input and output samples. An experimental implementation of the proposed modulator has been integrated in a 0.18-μm CMOS technology. Operating from a 1.8-V supply, it achieves a dynamic range of 90.1 dB and a peak signal-to-noise and distortion ratio (SNDR) of 86.3 dB at a conversion rate of 1 MSample/s, with 38.1-mW power consumption.
108 citations
TL;DR: This paper presents a 20-b read-out IC with ±40-mV full-scale range that is intended for use with bridge transducers and uses bulk-biasing and impedance-balancing techniques to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gain accuracy.
Abstract: This paper presents a 20-b read-out IC with ±40-mV full-scale range that is intended for use with bridge transducers. It consists of a current-feedback instrumentation amplifier (CFIA) followed by a switched-capacitor incremental ΔΣ ADC. The CFIA's offset and 1/f noise are mitigated by chopping, while its gain accuracy and gain drift are improved by applying dynamic element matching to its input and feedback transconductors. Their mismatch is reduced by a digitally assisted correction loop, which further reduces the CFIA's gain drift. Finally, bulk-biasing and impedance-balancing techniques are used to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gain accuracy. The combination of these techniques enables the read-out IC to achieve 140-dB CMRR, a worst-case gain error of 0.04% over a 0-2.5 V common-mode range, a maximum gain drift of 0.7 ppm/°C and an INL of 5 ppm. After applying nested-chopping, the read-out IC achieves 50-nV offset, 6-nV/°C offset drift, a thermal noise floor of 16.2 nV/√Hz and a 0.1-mHz 1/f noise corner. Implemented in a 0.7-μm CMOS technology, the prototype read-out IC consumes 270 μA from a 5-V supply.
76 citations
Cites background from "A low-power 22-bit incremental ADC"
...modulator, which employs feedforward topology to relax the linearity and slewing requirements of the integrators [21]....
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TL;DR: This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems that can achieve high-resolution without sacrificing the conversion rate by using two continuous-time incremental sigma-delta ADCs in a pipeline configuration.
Abstract: This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 $\mu{\rm m}$ CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 $\mu{\rm W}$ , which corresponds to a figure-of-merit of 0.85 pJ/conv.
71 citations
References
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Book•
08 Nov 2004
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
2,200 citations
"A low-power 22-bit incremental ADC" refers methods in this paper
...Finally, Section VII summarizes the design techniques and experimental results....
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TL;DR: A class of digital linear phase finite impulse response (FIR) filters for decimation and interpolation and use limited storage making them an economical alternative to conventional implementations for certain applications.
Abstract: A class of digital linear phase finite impulse response (FIR) filters for decimation (sampling rate decrease) and interpolation (sampling rate increase) are presented. They require no multipliers and use limited storage making them an economical alternative to conventional implementations for certain applications. A digital filter in this class consists of cascaded ideal integrator stages operating at a high sampling rate and an equal number of comb stages operating at a low sampling rate. Together, a single integrator-comb pair produces a uniform FIR. The number of cascaded integrator-comb pairs is chosen to meet design requirements for aliasing or imaging error. Design procedures and examples are given for both decimation and interpolation filters with the emphasis on frequency response and register width.
1,372 citations
"A low-power 22-bit incremental ADC" refers methods in this paper
...It uses a low-distortion configuration, in which the SC integrators (ideally) do not carry the input signal, so that the required linearity of the operational amplifiers (opamps) is reduced [6, ch. 3]....
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...Finally, Section VII summarizes the design techniques and experimental results....
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TL;DR: In this paper, a two-stage CMOS operational amplifier is proposed to provide stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit.
Abstract: The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.
521 citations
"A low-power 22-bit incremental ADC" refers background in this paper
...To keep the signal flow unchanged, the nonoverlapping phases and of the four input switches are also interchanged when INV is high....
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TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Abstract: Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.
269 citations
"A low-power 22-bit incremental ADC" refers background or methods in this paper
...Fig. 2. Block diagram of the delta-sigma loop. sinc filter [ 4 ]....
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...CMOS process based on the theory described in [ 4 ]....
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...The design theory of higher order IDCs was discussed in [ 4 ], which also discussed the tradeoffs between various realizations....
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...The minimum value of is determined by two conditions: the first insures the required accuracy of the delta-sigma modulator output signal, and the second requires the filling of the registers of the sinc filter with valid data [ 4 ]....
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TL;DR: In this paper, a simple and robust instrumentation A/D converter, fabricated in a low-voltage 4/spl mu/m CMOS technology, is described, and the measured overall accuracy was 16 bits.
Abstract: A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.
158 citations
"A low-power 22-bit incremental ADC" refers background or methods in this paper
...Dual-slope ADCs, on the other hand, are capable of low-offset and accurate gain operation, and do not need elaborate digital filters, but require a very long conversion time, and are sensitive to analog element nonidealities....
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...It operates for a predetermined number of clock periods (usually, is 1000–10 000), and is then reset....
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...Digital Object Identifier 10.1109/JSSC.2006.873891 In contrast to the conventional delta-sigma ADC, which converts a waveform operating continuously, the IDC converts individual input samples....
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