A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system

doi:10.1109/ISCAS.2006.1693458

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A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system

Proceedings Article•DOI•

A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system

H. Adrang¹, Reza Lotfi¹, K. Mafinejhad¹, A. Tajalli, S. Mehrmanesh - Show less +1 more•Institutions (1)

Ferdowsi University of Mashhad¹

21 May 2006-pp 4

TL;DR: The nonlinear behavior of the filter caused by non linear behavior of transconductors with determined input amplitude is discussed, and a new technique to enhance the linearity of the Gm-C filter is proposed.

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Abstract: In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18 /spl mu/m CMOS process show a THD of less than -44dB for 0.6V/sub pp/ input signal and an input-referred noise of less than 45 nV//spl radic/Hz in worst case. The current consumption of each OTA is 1.5-mA.

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Open Access

More filters

Journal Article•DOI•

Design of a new low power MISO multi-mode universal biquad OTA-C filter

[...]

Mostafa Parvizi¹•Institutions (1)

Islamic Azad University¹

04 Mar 2019-International Journal of Electronics

TL;DR: A new low-power multiple-input, single-output (MISO) multi-mode universal biquad operational transconductance amplifier-capacitor (OTA-C) filter with a minimum number of active and passive components is proposed and sensitivity analysis shows that the proposed filter has a low sensitivity to the values of the active and Passive elements.

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Abstract: In this article, a new low-power multiple-input, single-output (MISO) multi-mode universal biquad operational transconductance amplifier-capacitor (OTA-C) filter with a minimum number of active and passive components is proposed. The proposed filter employs three OTAs, one inverter and two grounded capacitors. The proposed filter can realise all filter frequency responses including low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) in all operation modes including voltage, current, tranasresistance and transconductance modes using the same topology. Furthermore, sensitivity analysis is done which shows that the proposed filter has a low sensitivity to the values of the active and passive elements. The proposed filter is simulated in HSPICE using 0.18 µm CMOS technology. The HSPICE simulation results demonstrate that the proposed filter consumes only 35 μW at 2.5 MHz from a ±0.5 V supply voltage, while all of the transistors are biased in strong inversion region. Also, ...

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14 citations

Cites methods from "A low-power CMOS Gm-C filter for wi..."

...In recent years, the OTA-C filters are used in many applications such as wireless receiver (Adrang et al., 2006), portable ECG (Lee & Cheng, 2009) and EEG (Casson & Rodriguez-Villegas, 2011) systems, mobile (Lakshmi & Vanathi, 2010), etc. Anyway, the OTA is a key circuit for analogue circuit design such as analogue continuous-time filters (Carrillo, Torelli, & Duque-Carrillo, 2011; Pedro et al., 2012; Zhang & El-Masry, 2007; Zhang, Zhang, & El-Masry, 2008) and analogue discrete-time filters (Chilakapati, Fiez, & Eshraghi, 2002; Lopez-Martin, Baswa, & Carvajal, 2005). Performance filtering frequency responses such as low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) as well as specifications such as power consumption and chip area are the main issues in analogue continuous-time filters for many applications. The main advantage of the universal filters is the ability of realizing all standard filtering frequency responses including LP, BP and HP. So the universal filter is preferable because it will cause a smaller size of the filter circuits (Jeshvaghani & Dolatshahi, 2014) that is very suitable for IC implementation. By mixing the inverting or non-inverting of the LP and HP filtering frequency responses in the output node, a filter can realise the BS filtering frequency response. Furthermore, if all of the standard filtering frequency responses collect together in the output node, a filter can realise the AP filtering frequency response. The universal filters reported by Lee and Liao (2008), Chen, Shen, and Wang (2008) employ two OTAs, one differential difference current conveyor (DDCC) and two capacitors. The universal filter proposed by Lee and Liao (2008) consists of 129 transistors, has a centre frequency of 2.18 MHz and consumes 83 mW but cannot realise the BS and AP filtering frequency responses. The two floating capacitors in the universal filter proposed by Chen et al. (2008) cause increased noise. The universal current mode filter proposed by Chen (2013) employs three dual-output current conveyors (DO-CCIIs), three grounded resistors and two grounded capacitors. The main drawback of this circuit is using three resistors which increase the noise and occupy more area on the chip. The universal filters proposed by Tangsrirat (2008) and Chang (2006) for realising different filtering frequency responses need to use a digitally programmable technique. This technique using some switches causes increased switching noise (Parvizi et al., 2017). Anyway, several universal OTA-C (Gm-C) filters have been reported by Parvizi et al. (2017), Jeshvaghani and Dolatshahi (2014), Tangsrirat (2008), Chang (2006), Chang and Pai (2000), Kumngern, Knobnob, and Dejhan (2010), Chang and Al-Hashimi (2003), Chunhua, Ling, and Tao (2008), Kumngern and Junnapiya (2012), Lee (2010), Abuelma’atti and Bentrcia (2006), Chen, Liao, and Lee (2009) and Namdari and Dolatshahi (2017)....
[...]
...In recent years, the OTA-C filters are used in many applications such as wireless receiver (Adrang et al., 2006), portable ECG (Lee & Cheng, 2009) and EEG (Casson & Rodriguez-Villegas, 2011) systems, mobile (Lakshmi & Vanathi, 2010), etc. Anyway, the OTA is a key circuit for analogue circuit design such as analogue continuous-time filters (Carrillo, Torelli, & Duque-Carrillo, 2011; Pedro et al., 2012; Zhang & El-Masry, 2007; Zhang, Zhang, & El-Masry, 2008) and analogue discrete-time filters (Chilakapati, Fiez, & Eshraghi, 2002; Lopez-Martin, Baswa, & Carvajal, 2005). Performance filtering frequency responses such as low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) as well as specifications such as power consumption and chip area are the main issues in analogue continuous-time filters for many applications. The main advantage of the universal filters is the ability of realizing all standard filtering frequency responses including LP, BP and HP. So the universal filter is preferable because it will cause a smaller size of the filter circuits (Jeshvaghani & Dolatshahi, 2014) that is very suitable for IC implementation. By mixing the inverting or non-inverting of the LP and HP filtering frequency responses in the output node, a filter can realise the BS filtering frequency response. Furthermore, if all of the standard filtering frequency responses collect together in the output node, a filter can realise the AP filtering frequency response. The universal filters reported by Lee and Liao (2008), Chen, Shen, and Wang (2008) employ two OTAs, one differential difference current conveyor (DDCC) and two capacitors. The universal filter proposed by Lee and Liao (2008) consists of 129 transistors, has a centre frequency of 2.18 MHz and consumes 83 mW but cannot realise the BS and AP filtering frequency responses. The two floating capacitors in the universal filter proposed by Chen et al. (2008) cause increased noise. The universal current mode filter proposed by Chen (2013) employs three dual-output current conveyors (DO-CCIIs), three grounded resistors and two grounded capacitors. The main drawback of this circuit is using three resistors which increase the noise and occupy more area on the chip. The universal filters proposed by Tangsrirat (2008) and Chang (2006) for realising different filtering frequency responses need to use a digitally programmable technique....
[...]
...In recent years, the OTA-C filters are used in many applications such as wireless receiver (Adrang et al., 2006), portable ECG (Lee & Cheng, 2009) and EEG (Casson & Rodriguez-Villegas, 2011) systems, mobile (Lakshmi & Vanathi, 2010), etc. Anyway, the OTA is a key circuit for analogue circuit design such as analogue continuous-time filters (Carrillo, Torelli, & Duque-Carrillo, 2011; Pedro et al., 2012; Zhang & El-Masry, 2007; Zhang, Zhang, & El-Masry, 2008) and analogue discrete-time filters (Chilakapati, Fiez, & Eshraghi, 2002; Lopez-Martin, Baswa, & Carvajal, 2005). Performance filtering frequency responses such as low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) as well as specifications such as power consumption and chip area are the main issues in analogue continuous-time filters for many applications. The main advantage of the universal filters is the ability of realizing all standard filtering frequency responses including LP, BP and HP. So the universal filter is preferable because it will cause a smaller size of the filter circuits (Jeshvaghani & Dolatshahi, 2014) that is very suitable for IC implementation. By mixing the inverting or non-inverting of the LP and HP filtering frequency responses in the output node, a filter can realise the BS filtering frequency response. Furthermore, if all of the standard filtering frequency responses collect together in the output node, a filter can realise the AP filtering frequency response. The universal filters reported by Lee and Liao (2008), Chen, Shen, and Wang (2008) employ two OTAs, one differential difference current conveyor (DDCC) and two capacitors. The universal filter proposed by Lee and Liao (2008) consists of 129 transistors, has a centre frequency of 2.18 MHz and consumes 83 mW but cannot realise the BS and AP filtering frequency responses. The two floating capacitors in the universal filter proposed by Chen et al. (2008) cause increased noise....
[...]
...In recent years, the OTA-C filters are used in many applications such as wireless receiver (Adrang et al., 2006), portable ECG (Lee & Cheng, 2009) and EEG (Casson & Rodriguez-Villegas, 2011) systems, mobile (Lakshmi & Vanathi, 2010), etc. Anyway, the OTA is a key circuit for analogue circuit design such as analogue continuous-time filters (Carrillo, Torelli, & Duque-Carrillo, 2011; Pedro et al., 2012; Zhang & El-Masry, 2007; Zhang, Zhang, & El-Masry, 2008) and analogue discrete-time filters (Chilakapati, Fiez, & Eshraghi, 2002; Lopez-Martin, Baswa, & Carvajal, 2005). Performance filtering frequency responses such as low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) as well as specifications such as power consumption and chip area are the main issues in analogue continuous-time filters for many applications. The main advantage of the universal filters is the ability of realizing all standard filtering frequency responses including LP, BP and HP. So the universal filter is preferable because it will cause a smaller size of the filter circuits (Jeshvaghani & Dolatshahi, 2014) that is very suitable for IC implementation. By mixing the inverting or non-inverting of the LP and HP filtering frequency responses in the output node, a filter can realise the BS filtering frequency response. Furthermore, if all of the standard filtering frequency responses collect together in the output node, a filter can realise the AP filtering frequency response. The universal filters reported by Lee and Liao (2008), Chen, Shen, and Wang (2008) employ two OTAs, one differential difference current conveyor (DDCC) and two capacitors....
[...]
...In recent years, the OTA-C filters are used in many applications such as wireless receiver (Adrang et al., 2006), portable ECG (Lee & Cheng, 2009) and EEG (Casson & Rodriguez-Villegas, 2011) systems, mobile (Lakshmi & Vanathi, 2010), etc. Anyway, the OTA is a key circuit for analogue circuit design such as analogue continuous-time filters (Carrillo, Torelli, & Duque-Carrillo, 2011; Pedro et al., 2012; Zhang & El-Masry, 2007; Zhang, Zhang, & El-Masry, 2008) and analogue discrete-time filters (Chilakapati, Fiez, & Eshraghi, 2002; Lopez-Martin, Baswa, & Carvajal, 2005). Performance filtering frequency responses such as low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) as well as specifications such as power consumption and chip area are the main issues in analogue continuous-time filters for many applications. The main advantage of the universal filters is the ability of realizing all standard filtering frequency responses including LP, BP and HP. So the universal filter is preferable because it will cause a smaller size of the filter circuits (Jeshvaghani & Dolatshahi, 2014) that is very suitable for IC implementation. By mixing the inverting or non-inverting of the LP and HP filtering frequency responses in the output node, a filter can realise the BS filtering frequency response. Furthermore, if all of the standard filtering frequency responses collect together in the output node, a filter can realise the AP filtering frequency response. The universal filters reported by Lee and Liao (2008), Chen, Shen, and Wang (2008) employ two OTAs, one differential difference current conveyor (DDCC) and two capacitors. The universal filter proposed by Lee and Liao (2008) consists of 129 transistors, has a centre frequency of 2.18 MHz and consumes 83 mW but cannot realise the BS and AP filtering frequency responses. The two floating capacitors in the universal filter proposed by Chen et al. (2008) cause increased noise. The universal current mode filter proposed by Chen (2013) employs three dual-output current conveyors (DO-CCIIs), three grounded resistors and two grounded capacitors....
[...]

Journal Issue•DOI•

Analysis of OTA-C filters with weakly nonlinear transconductors

[...]

Slawomir Koziel¹•Institutions (1)

McMaster University¹

01 Oct 2008-International Journal of Circuit Theory and Applications

TL;DR: In this article, an algebraic description of a general OTA-C filter structure is presented, based on which an efficient approach for analysis of nonlinear distortion in OTA -C filters with weakly nonlinear transconductors is presented.

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Abstract: An efficient approach for analysis of nonlinear distortion in OTA-C filters with weakly nonlinear transconductors is presented. The procedure is developed based on an algebraic description of a general OTA-C filter structure and, therefore, the results are valid for any filter architecture within OTA-C class. On the basis of the proposed method, explicit formulas for calculating a gain compression-expansion ratio in an arbitrary OTA-C filter are developed. The formulas are easy to implement and use in computer-aided filter design tools. For illustration purposes, several filter structures are considered. The accuracy of the method is verified by comparing the results with the exact values of gain compression-expansion ratio achieved by integrating the differential system that determines the time response of OTA-C filter. The presented approach can be generalized in order to consider other nonlinear parameters. Copyright © 2007 John Wiley & Sons, Ltd.

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8 citations

Journal Article•DOI•

A pseudo differential G m —C complex filter with frequency tuning for IEEE802.15.4 applications

[...]

Cheng Xin¹, Zhong Lungui², Yang Haigang¹, Liu Fei¹, Gao Tongqiang¹ - Show less +1 more•Institutions (2)

Chinese Academy of Sciences¹, Fujian University of Technology²

01 Jul 2011-Journal of Semiconductors

TL;DR: In this article, a CMOS Gm-C complex filter for a low-IF receiver of the IEEE 802.15.4 standard has been presented, where a pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator.

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Abstract: This paper presents a CMOS Gm—C complex filter for a low-IF receiver of the IEEE 802.15.4 standard. A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator. A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated. The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately. The chip was fabricated in a standard 0.35 μm CMOS process, with a single 3.3 V power supply. The filter consumes 2.1mA current, has a measured in-band group delay ripple of less than 0.16 μs and an IRR larger than 28 dB at 2 MHz apart, which could meet the requirements oftheIEEE802.15.4 standard.

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4 citations

Journal Article•DOI•

Capacitance Reduction Technique for Switched-Capacitor Circuits Based on Charge Distribution and Partial Charge Transfer

[...]

Retdian Agung Nicodimus¹, Shigetaka Takagi¹•Institutions (1)

Tokyo Institute of Technology¹

01 Feb 2011-IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

TL;DR: The proposed technique is based on a simple charge distribution and partial charge transfer which is applicable to various integrator topologies and has an approximately 23% less total capacitance than the one of SC low-pass filter with conventional capacitance spread reduction technique.

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Abstract: This paper proposes a technique to reduce the capacitance spread in switched-capacitor (SC) filters. The proposed technique is based on a simple charge distribution and partial charge transfer which is applicable to various integrator topologies. An implementation example on an existing integrator topology and a design example of a 2nd-order SC low-pass filter are given to demonstrate the performance of the proposed technique. A design example of an SC filter show that the filter designed using the proposed technique has an approximately 23% less total capacitance than the one of SC low-pass filter with conventional capacitance spread reduction technique.

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4 citations

Proceedings Article•DOI•

Capacitance spread reduction technique for low-cost switched-capacitor filters implementation

[...]

Nicodimus Retdian¹, Katsuyuki Takagi¹, Shigetaka Takagi¹•Institutions (1)

Tokyo Institute of Technology¹

02 Oct 2009

TL;DR: The proposed technique is based on a simple charge distribution and a partial charge transfer techniques, and is applicable to various integrator topologies and is found to be insensitive to parasitic capacitances.

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Abstract: This paper proposes a technique to reduce capacitance spread in switched-capacitor filters. The proposed technique is based on a simple charge distribution and a partial charge transfer techniques, and is applicable to various integrator topologies. Simulation results show that the proposed technique reduces the total capacitance by 70%, which is a significant reduction of filter area. Furthermore, an integrator implemented by the proposed technique is found to be insensitive to parasitic capacitances.

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3 citations

References

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Open Access

More filters

Journal Article•DOI•

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

[...]

Francois Krummenacher, N. Joehl

01 Jun 1988-IEEE Journal of Solid-state Circuits

TL;DR: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process, based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.

...read moreread less

Abstract: A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3- mu m p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD >

...read moreread less

652 citations

"A low-power CMOS Gm-C filter for wi..." refers methods in this paper

...The linearization methods include cross-coupling of multiple differential pairs [3], [4] adaptive biasing [3], [5] source degeneration [6], [7] and pseudo-differential stages (using transistor in the triode region or in saturation) [8]....
[...]

Proceedings Article•

A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning

[...]

Francois Krummenacher¹, N. Joehl¹•Institutions (1)

École Polytechnique Fédérale de Lausanne¹

01 Sep 1987

TL;DR: In this article, a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3?m CMOS process, is presented, based on direct simulation of a doublyterminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range.

...read moreread less

Abstract: This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 ?m CMOS process. The design approach is based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range. PLL techniques, involving a 8.5 MHz controlled oscillator that matches a specific part of the filter, are used to realize on-chip automatic tuning. The complete circuit features 71 dB dynamic range and consumes only 16 mW from a single 5 V supply.

...read moreread less

644 citations

Journal Article•DOI•

Design of linear CMOS transconductance elements

[...]

A. Nedungadi¹, T. Viswanathan²•Institutions (2)

Texas A&M University¹, University of Waterloo²

01 Jan 1984-IEEE Transactions on Circuits and Systems

TL;DR: In this paper, some novel circuit techniques for realizing linear CMOS tranconductance elements are proposed, which have superior linearity and input voltage range compared with the conventional source-coupled differential pair.

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Abstract: Some novel circuit techniques for realizing linear CMOS tranconductance elements are proposed. The circuits discussed have superior linearity and input voltage range compared with the conventional source-coupled differential pair. Design tradeoffs are examined and computer simulation results are used to verify theoretical predictions. The results show close agreement between predicted behavior and simulated performance.

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343 citations

Journal Article•DOI•

A versatile CMOS linear transconductor/square-law function

[...]

E. Seevinck¹, R.F. Wassenaar¹•Institutions (1)

University of Twente¹

01 Jun 1987-IEEE Journal of Solid-state Circuits

TL;DR: A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described, which is versatile in application and diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

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Abstract: A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.

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327 citations

"A low-power CMOS Gm-C filter for wi..." refers methods in this paper

...The linearization methods include cross-coupling of multiple differential pairs [3], [4] adaptive biasing [3], [5] source degeneration [6], [7] and pseudo-differential stages (using transistor in the triode region or in saturation) [8]....
[...]

Journal Article•DOI•

Adaptive biasing CMOS amplifiers

[...]

M. Degrauwe¹, J. Rijmenants¹, Eric A. Vittoz, H.J. De Man¹•Institutions (1)

Katholieke Universiteit Leuven¹

01 Jun 1982-IEEE Journal of Solid-state Circuits

TL;DR: In this paper, two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced, and the amplifiers combine a very low standby power dissipation with a high driving capability.

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Abstract: Two transconductance amplifiers are presented in which the concept of an input dependent bias current has been introduced. As a result, these amplifiers combine a very low standby power dissipation with a high driving capability. The first amplifier, suited for SC filters, is fairly small (0.075 mm/SUP 2/) and has a slew rate which is more than an order of magnitude better than micropower amplifiers presented earlier. The second amplifier can be used as a micropower buffer. Nearly the whole supply current is used to charge the load capacitor so that this amplifier has a high efficiency.

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284 citations

"A low-power CMOS Gm-C filter for wi..." refers methods in this paper

...The linearization methods include cross-coupling of multiple differential pairs [3], [4] adaptive biasing [3], [5] source degeneration [6], [7] and pseudo-differential stages (using transistor in the triode region or in saturation) [8]....
[...]