A low-power, high-performance, 1024-point FFT processor
Citations
619 citations
Cites background from "A low-power, high-performance, 1024..."
...Dedicated low-power FFT processors are desired to sustain low-power requirements of various embedded applications [11]....
[...]
270 citations
220 citations
Cites background from "A low-power, high-performance, 1024..."
...Various FFT architectures, such as single-memory architecture, dual-memory architecture [2], pipelined architecture [3], array architecture [4], and cached-memory architecture [5], have been proposed in the last three decades....
[...]
196 citations
Cites background or methods from "A low-power, high-performance, 1024..."
...format requires the eventual truncation of the butterfly outputs when writing the outputs back to memory, computation of all the multiplier output bits is unnecessary [23]....
[...]
...The processor’s datapath computes one complex radix-2 DIT butterfly per cycle [23]....
[...]
143 citations
Cites background from "A low-power, high-performance, 1024..."
...[2], pipelined architecture [3], array architecture [4], and cached-memory architecture [5], have been proposed....
[...]
References
11,671 citations
"A low-power, high-performance, 1024..." refers background in this paper
...It is well known that data caches increase the effective bandwidth to a memory—but only if the memory access pattern exhibits sufficient locality [ 10 ]....
[...]
10,388 citations
3,249 citations
2,690 citations
2,337 citations
"A low-power, high-performance, 1024..." refers background in this paper
...Unfortunately, a lower supply voltage reduces circuit performance....
[...]