A low-power high-speed comparator for analog to digital converters

doi:10.1109/ISCAS.2016.7538971

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A low-power high-speed comparator for analog to digital converters

Proceedings Article•DOI•

A low-power high-speed comparator for analog to digital converters

Ata Khorami¹, Mahmood Baraani Dastjerdi¹, Ali Ahmadi¹•Institutions (1)

Sharif University of Technology¹

22 May 2016-pp 2010-2013

TL;DR: Simulation results in 0.18 μm CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit.

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Abstract: A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power consumption of the comparator trades with the speed which is simply controlled by the delay of the second stage. As a result, a low-power comparator for given offset and speed requirements can be designed efficiently.

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Journal Article•DOI•

A Low-Power High-Speed Comparator for Precise Applications

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Ata Khorami¹, Mohammad Sharifkhani¹•Institutions (1)

Sharif University of Technology¹

16 May 2018-IEEE Transactions on Very Large Scale Integration Systems

TL;DR: A low-power comparator using pMOS transistors at the input of the preamplifier of the comparator as well as the latch stage that reduces the power consumption and provides 30% better comparison speed at the same offset and almost the same noise budgets.

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Abstract: A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified using solid analytical derivations, process–VDD–temperature corners, and Monte Carlo simulations along with silicon measurements in $0.18~\mu \text{m}$ . The tests confirm that the proposed circuit reduces the power consumption by 50% and provides 30% better comparison speed at the same offset and almost the same noise budgets. Moreover, the comparator provides a rail-to-rail input $V_{\text {cm}}$ range in $f_{\text {clk}} = 500$ MHz.

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57 citations

Proceedings Article•DOI•

Fully Synthesizable, Rail-to-Rail Dynamic Voltage Comparator for Operation down to 0.3 V

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Orazio Aiello¹, Paolo Stefano Crovetti², Massimo Alioto¹•Institutions (2)

National University of Singapore¹, Polytechnic University of Turin²

27 May 2018

TL;DR: The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain.

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Abstract: A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltage VDD down to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (around VDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications.

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25 citations

Cites background from "A low-power high-speed comparator f..."

...In detail, one of the major drawbacks of the DVC in [4] is its very narrow common-mode input range (CMR), which makes it unusable in many circuits that require a DVC, such as Flash ADCs and successiveapproximation-register (SAR) ADCs featuring energy-efficient switching schemes [7], where the common-mode (CM) input voltage is not constant....
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...Parameters This work [3] [4] [5] Design flow fully digital analog analog fully digital Technology CMOS 40nm CMOS 130nm CMOS 180nm CMOS 40nm Area [μm ] 62 N/A N/A 35 V [V] 0....
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..., [2-4]), their supply voltage is typically 0....
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Journal Article•DOI•

Excess power elimination in high-resolution dynamic comparators

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Ata Khorami¹, Mohammad Sharifkhani¹•Institutions (1)

Sharif University of Technology¹

01 Jun 2017-Microelectronics Journal

TL;DR: It is shown that while reducing the power consumption significantly, the method does not affect the dynamic behavior of the comparator such as speed or offset voltage.

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22 citations

Journal Article•DOI•

A low-power technique for high-resolution dynamic comparators

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Ata Khorami¹, Mohammad Sharifkhani¹•Institutions (1)

Sharif University of Technology¹

01 Oct 2018-International Journal of Circuit Theory and Applications

15 citations

Cites background or methods from "A low-power high-speed comparator f..."

...Comparators are at the heart of different types of ADCs, such as Sucessive Approximation Register (SAR), pipeline, and flash ADCs.1-22 These days, dynamic comparators are widely being used because of their low‐power consumption.1 In fact, in these comparators, usually there is no constant (current) path from the supply voltage to Vss, and they are controlled by a clock signal....
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...Consequently, the proposed technique is an effective solution for low‐power high‐resolution ADCs, especially for those high‐resolution ADCs using multiple comparators, such as the ADC's reported in other studies.19-21 In fact, in 2 bit/step SAR ADCs, flash ADCs, and pipeline ADCs comparators play a critical role in the total performance of the circuit, and their performance is efficiently improved by the proposed comparator....
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...Comparators are at the heart of different types of ADCs, such as Sucessive Approximation Register (SAR), pipeline, and flash ADCs.(1-22) These days, dynamic comparators are widely being used because of their low‐power consumption....
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...Power efficient analog‐to‐digital converters (ADCs) are the key building blocks of different modules, such as communication systems and biomedical implants....
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...ic t ð Þ 1⁄4 C dvc t ð Þ dt ⇒ ic t ð Þ : dt 1⁄4 C : dvc t ð Þ (21)...
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Proceedings Article•DOI•

HDC-IM: Hyperdimensional Computing In-Memory Architecture based on RRAM

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Jialong Liu¹, Mingyuan Ma¹, Zhenhua Zhu¹, Yu Wang¹, Huazhong Yang¹ - Show less +1 more•Institutions (1)

Tsinghua University¹

01 Nov 2019

TL;DR: HDC-IM is proposed, a Hyperdimensional Computing-In-Memory architecture based on Resistive Random-Access Memory (RRAM), to boost the energy efficiency of HDC and is more fault-tolerant taking into account RRAM device faults.

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Abstract: Brain-inspired Hyperdimensional Computing (HDC) is a fast and robust classification algorithm, which works by mapping low-dimensional features to high-dimensional vectors and comparing distance in a high dimensional space. However, in traditional Von Neumann architecture, HDC causes high energy consumption because of large data movements between processor and memory. In this paper, we propose HDC-IM, a Hyperdimensional Computing-In-Memory architecture based on Resistive Random-Access Memory (RRAM), to boost the energy efficiency of HDC. HDC-IM puts computations in or near memory, which eliminates most of the data movements, providing a solution to reduce the energy consumption. In addition, to improve the computing parallelism, we use in-crossbar RRAM-based logic design to process encoding operation in HDC. The experimental results show that HDC-IM provides more than 100× speedup and higher energy efficiency compared with HDC on CPU. Moreover, in comparison with existing RRAM-based Neural Network accelerators, HDC-IM is more fault-tolerant taking into account RRAM device faults, achieving 20% higher accuracy than RRAM-based DNN on ISOLET dataset when 20% RRAM devices suffer from Stuck-At-Faults (SAFs).

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11 citations

Cites methods from "A low-power high-speed comparator f..."

...The parameters we used refer to [9] [10] [11] [12] [14]....
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Journal Article•DOI•

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

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Thomas Byunghak Cho¹, Paul R. Gray¹•Institutions (1)

University of California, Berkeley¹

01 Mar 1995-IEEE Journal of Solid-state Circuits

TL;DR: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.

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Abstract: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >

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623 citations

Proceedings Article•

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

[...]

Thomas Byunghak Cho, Paul R. Gray

01 Jan 1995

TL;DR: In this article, the authors describe a 10 b, 20 µm pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation.

...read moreread less

Abstract: ―This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB. Differential input range is ± 1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR.

...read moreread less

577 citations

Journal Article•DOI•

Design techniques for high-speed, high-resolution comparators

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Behzad Razavi¹, Bruce A. Wooley¹•Institutions (1)

Stanford University¹

01 Dec 1992-IEEE Journal of Solid-state Circuits

TL;DR: In this article, precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described, and circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented.

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Abstract: Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 mu V at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 mu V at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW. >

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533 citations

"A low-power high-speed comparator f..." refers background in this paper

...Nowadays, low-power design is the main trend in the design of electronic circuits [1]-[10]....
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...In these comparators the first stage, pre-amplifier stage, amplifies the input differential signal, then the second stage, latch stage, amplifies its input differential voltage until reaches V dd and Gnd [1]....
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...If the amplification gain of the first stage is large enough, the effect of second stage on the offset voltage is negligible [1]....
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...In this circuit, the amplified input differential signal appears at the output of the pre-amplifier stage, then the latch stage amplifies its input signal until its output voltages settle at V dd and Gnd....
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...This situation takes place when the common mode voltage of the input signals is low, close to Gnd....
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Journal Article•DOI•

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

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Michiel van Elzakker¹, Ed van Tuijl¹, P.F.J. Geraedts¹, Daniel Schinkel¹, Eric A.M. Klumperink¹, Bram Nauta¹ - Show less +2 more•Institutions (1)

University of Twente¹

01 May 2010-IEEE Journal of Solid-state Circuits

TL;DR: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller.

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Abstract: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

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377 citations

"A low-power high-speed comparator f..." refers background or methods in this paper

...Nowadays, low-power design is the main trend in the design of electronic circuits [1]-[10]....
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...control signals are implemented using a delay line based controller [10]....
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Journal Article•DOI•

Kickback noise reduction techniques for CMOS latched comparators

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P.M. Figueiredo, J.C. Vital

17 Jul 2006-IEEE Transactions on Circuits and Systems Ii-express Briefs

TL;DR: This brief reviews existing solutions to minimize the kickback noise and proposes two new ones and HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

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Abstract: The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

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324 citations