A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier
01 Nov 2018-pp 99-100
TL;DR: The proposed design with the signal folding technique has adequately minimized the total power consumption and performance metrics such as gain, bandwidth, and input referred noise is also finely optimized.
Abstract: This paper proposes a design of low-power and low-noise CMOS neural recording amplifier with an open-loop configuration. The proposed design has been simulated using CMOS 0.18µm process. The proposed design with the signal folding technique, when compared to the closed-loop configured neural amplifier, has adequately minimized the total power consumption. The performance metrics such as gain, bandwidth, and input referred noise is also finely optimized.
Citations
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TL;DR: A novel design for ultra-low noise neural recording amplifier that achieves a gain of 43.6dB with a total power consumption of 26.29μW and input-referred noise of 313.6pVrms is discussed.
Abstract: Introduction: In recent years, neural system study has become a fruitful approach in diagnosing neurological diseases. Brain signals being at very low potentials pose a difficulty to study them. Fault analysis of those signals may lead to improper diagnosis of the diseases. So, amplification of the brain signal is required. The amplified signal is prone to noise. Objective: To meet the limitations of the neural acquisition system a novel design for ultra-low noise neural recording amplifier is discussed in this paper. Methods: Characterization of transistors is the technique used to design the amplifier. The amplifier is designed in a standard 0.18μm Complementary metal oxide semiconductor process (CMOS). Results: The amplifier achieved a gain of 43.6dB with a total power consumption of 26.29μW and input-referred noise of 313.6pVrms.
References
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TL;DR: In this article, a low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface is presented.
Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.
1,572 citations
"A Low-power Low-noise Open-loop Con..." refers background or methods in this paper
...Two comparators as in [1] are used in the design and the comparator design, shown in Fig....
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...From the obtained parameters, common mode rejection ratio (CMRR) and the noise efficiency factor (NEF) are calculated as in [1]....
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...INTRODUCTION Recent works on neural recording integrated circuits (ICs) have improved the quality of capturing the electrical activity of neurons [1]–[3] and therefore the performance of neural recording applications were also improved [4]–[6]....
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TL;DR: An activity-dependent intracortical microstimulation (ICMS) system-on-chip (SoC) that converts extracellular neural spikes recorded from one brain region to electrical stimuli delivered to another brain region in real time in vivo is described.
Abstract: This paper describes an activity-dependent intracortical microstimulation (ICMS) system-on-chip (SoC) that converts extracellular neural spikes recorded from one brain region to electrical stimuli delivered to another brain region in real time in vivo. The 10.9-mm2 SoC incorporates two identical 4-channel modules, each comprising an analog recording front-end with total input noise voltage of 3.12 μVrms and noise efficiency factor (NEF) of 2.68, 5.9-μW 10-bit successive approximation register analog-to-digital converters (SAR ADCs), 12.4-μW digital spike discrimination processor, and a programmable constant-current microstimulating back-end that delivers up to 94.5 μA with 6-bit resolution to stimulate the cortical tissue when triggered by neural activity. For autonomous operation, the SoC also integrates biasing and clock generation circuitry, frequency-shift-keyed (FSK) transmitter at 433 MHz, and dc-dc converter that generates a power supply of 5.05 V for the microstimulating back-end from a single 1.5-V battery. Measured results from electrical performance characterization and biological experiments with anesthetized rats are presented from a prototype chip fabricated in AMS 0.35 μm two-poly four-metal (2P/4M) CMOS. A noise analysis for the selected low-noise amplifier (LNA) topology is presented that obtains a minimum NEF of 2.33 for a practical design given the technology parameters and power supply voltage. Future considerations in the SoC design with respect to silicon area and power consumption when increasing the number of channels are also discussed.
167 citations
27 May 2007
TL;DR: A fully differential low-power low-noise preamplifier with multiple adjustable parameters for biopotential and neural recording applications and common mode feedback has been utilized to guarantee the amplifier functionality by forcing the output DC level to a desired voltage.
Abstract: We have developed a fully differential low-power low-noise preamplifier with multiple adjustable parameters for biopotential and neural recording applications. Common mode feedback has been utilized to guarantee the amplifier functionality by forcing the output DC level to a desired voltage. A switch is added to the output to achieve fast settling time in case the amplifier is saturated. The amplifier has been implemented in the AMI 1.5-mum 2M2P standard CMOS process and occupies 0.201 mm2 on chip. The amplifier current consumption is 8 muA at plusmn1.7 V supply, with two measured AC gains of 39.3 dB and 45.6 dB. The low cutoff frequency is 4-bit programmable from 0.015 Hz to 700 Hz. The high cutoff frequency can be adjusted from 120 Hz to 12 kHz at negligible load and 40 Hz to 4 kHz with a 2 pF active probe loading. The measured input referred noise is 3.6 muV over 20 Hz ~ 10 kHz. The amplifier also provides rail-to-rail input DC range, maximum input offset of 0.7 mV, common mode tuning range of plusmn600 mV, and output swing of plusmn0.9 V with minimum distortion.
143 citations
TL;DR: This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson's disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems.
Abstract: This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson's disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circuits for data telemetry that minimize power consumption of implanted systems in the body; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons with power-conserving sleep modes and awake modes. Experimental results from chips that have stimulated and recorded from neurons in the zebra finch brain and results from RF power-link, RF data-link, electrode-recording and electrode-stimulating systems are presented. Simulations of analog learning circuits that have successfully decoded prerecorded neural signals from a monkey brain are also presented.
107 citations
"A Low-power Low-noise Open-loop Con..." refers background in this paper
...INTRODUCTION Recent works on neural recording integrated circuits (ICs) have improved the quality of capturing the electrical activity of neurons [1]–[3] and therefore the performance of neural recording applications were also improved [4]–[6]....
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TL;DR: A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/fn characteristics of neural signals is described in this paper, which enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range.
Abstract: A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.
41 citations
"A Low-power Low-noise Open-loop Con..." refers background in this paper
...INTRODUCTION Recent works on neural recording integrated circuits (ICs) have improved the quality of capturing the electrical activity of neurons [1]–[3] and therefore the performance of neural recording applications were also improved [4]–[6]....
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...2(b) which is similar to [3] but has an open-loop configuration and OTA with single-stage topology....
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...It is the same as in [3] except the operational transconductance amplifier (OTA) with single-stage topology....
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