A low power preamplifier latch based comparator using 180nm CMOS technology
01 Dec 2013-pp 208-212
TL;DR: This paper mainly focuses on the preamplifier positive feedback latch based comparator for Asynchronous Successive Approximation Register ADC (ASAR ADC), which credits to the least power dissipation in the circuitry which was designed in 180nm CMOS technology.
Abstract: Design of high speed low power comparators are required to build an efficient analog to digital converters (ADCs). This paper mainly focuses on the preamplifier positive feedback latch based comparator for Asynchronous Successive Approximation Register ADC (ASAR ADC). The main components of such comparator are the preamplifier and latch circuit. Preamplifier is used for removing the kickback noise and the dc offset voltage while the latch is required for the comparison. The proposed architecture operates on three phases which are non overlapping and dissipates 70μWpower when operated on a single 1V supply voltage. The latch is basically a back to back connected inverter circuit which is activated only during the second phase. This specialty credits to the least power dissipation in the circuitry which was designed in 180nm CMOS technology.
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08 Jul 2015
TL;DR: An improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC is presented.
Abstract: High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC. The comparator has two different stages comprising of a dynamic differential input gain stage and an output latch. The objective of improving the speed of conversion is done by removing the dead time required for reset in the differential input stage. In the proposed work the output node in the differential gain stage requires lesser time to regain higher charge potential. The proposed methodology has been designed and simulated using 180nm CMOS technology operated on a single 1V power supply and achieves complete 8-bit conversion in 75nsec.
10 citations
Cites background from "A low power preamplifier latch base..."
...The complete working and description of this can be found from [9] [10]....
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01 Dec 2016
TL;DR: This work has designed a dynamic comparator consuming low power of 0.169uW and implemented encoder block using 2:1 MUX, which is having power dissipation of 7.2394mW and delay of 29.792ns.
Abstract: Among all the ADC architectures, Flash ADCs are the most preferred ones. High speed operation is the main reason for selecting Flash ADC. Applications which require high speed conversion in mixed mode signal processing needs Flash ADC. In order to have high speed Flash ADC, the design of comparators is the main task. Since comparators in Flash ADC are power hungry components, we should design each compactor in such a way that overall power consumption should be less. Here we have designed a dynamic comparator consuming low power of 0.169uW. Then we have implemented encoder block using 2:1 MUX. Using these components we have implemented 4-bit Flash ADC which is having power dissipation of 7.2394mW and delay of 29.792ns. The design is implemented in Mentor Graphics tool using 180nm Technology.
8 citations
Cites background from "A low power preamplifier latch base..."
...Because of the variation in the input applied, nodes discharges at different rates, this difference in discharging rate will produce a differential voltage say ΔV, dependent on input [5]....
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01 Sep 2016
TL;DR: It is shown that the proposed dynamic comparator has good tradeoff between power consumption and delay with same sampling frequency and is proposed by removing few transistors to the conventional double-tail dynamic comparators to maximize speed and reduce power consumption.
Abstract: The need for high speed and low power analog-to-digital converters is pushing towards the use of power efficient dynamic regenerative comparator. A complete delay analysis on the double-tail dynamic comparators will be presented. Based on the calculated analysis a new dynamic comparator has proposed by removing few transistors to the conventional double-tail dynamic comparator to maximize speed and reduce power consumption. It is shown that the proposed comparator has good tradeoff between power consumption and delay with same sampling frequency. The comparator fabricated in 180nm CMOS process with clock frequency of 450 MHz at supply voltage 1.2 V consumes power of 37 pW.
6 citations
Cites methods from "A low power preamplifier latch base..."
...Low power CMOS comparator is designed by using preamplifier and latch circuit in 180nm technology [6]....
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01 Dec 2014
TL;DR: The design is composed of a Comparator, Charge Scaling DAC and a digital SAR logic block and operated on a single 1 V power supply which dissipated a power of 32.419μW which is much lesser compared to the other existing architecture such as current scaling DAC and voltage scaling DAC.
Abstract: This paper instigates a "design of an 8-bit Asynchronous-Successive Approximation Register (ASAR) ADC (analog-to-digital converter) employing a Charge Scaling DAC (digital-to-analog converter)". The design itemizes the word asynchronous, which claims it to be independent of the external clock signal. The proposed design is composed of a Comparator, Charge Scaling DAC and a digital SAR logic block. The design was simulated using 180nm CMOS technology and operated on a single 1 V power supply which dissipated a power of 32.419a#x03BC;W which is much lesser compared to the other existing architecture such as current scaling DAC and voltage scaling DAC.
6 citations
Cites background from "A low power preamplifier latch base..."
...2 Circuitry of the complete Comparator [10] IV....
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...A detailed description and working of the preamplifier based latched comparator can be found in [10]....
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...Fig.1 Architectural view of the designed ASAR ADC Fig.2 Circuitry of the complete Comparator [10] IV....
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TL;DR: In this article , the authors surveyed various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit.
Abstract: In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators, cochlear implants, visual prosthesis etc. have gained immense importance in the personal health monitoring system. Most of these devices are battery powered. The life span of a pacemaker is expected to be between 10 and 12 years. This shows the importance of having an ultra-low power design technique to improve the reliability and battery life of the system. To achieve this, power draws from the battery must be kept low. Analog-to-Digital Convertor (ADC) is a main block in the front-end sensing unit of an implant for measurements of various biophysiological signals. This is the most power consuming unit in the system. ADC alone consumes about 30%–35% of the total power. This work surveys various successive approximation ADC designs for biomedical signal acquisition, in terms of power consumption, signal to noise distortion ratio, sampling rate, resolution and Figure of Merit. The different switching schemes for capacitive DAC are also surveyed.
4 citations
References
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Book•
01 Jan 1987
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Abstract: 1.1 ANALOG INTEGRATED CIRCUIT DESIGN 1.2 NOTATION, SYMBOLOGY AND TERMINOLOGY 1.3 ANALOG SIGNAL PROCESSING 1.4 EXAMPLE OF ANALOG VLSI MIXED-SIGNAL CIRCUIT DESIGN 2.1 BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES 2.2 THE PN JUNCTION 2.3 THE MOS TRANSISTOR 2.4 PASSIVE COMPONENTS 2.5 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY 3.1 SIMPLE MOS LARGE-SIGNAL MODEL (SPICE LEVEL 1) 3.2 OTHER MOS LARGE-SIGNAL MODEL PARAMETERS 3.3 SMALL-SIGNAL MODEL FOR THE MOS TRANSISTOR 3.4 COMPUTER SIMULATION MODELS 3.5 SUBTHRESHOLD MOS MODEL 3.6 SPICE SIMULATION OF MOS CIRCUITS 4.1 MOS SWITCH 4.2 MOS DIODE/ACTIVE RESISTOR 4.3 CURRENT SINKS AND SOURCES 4.4 CURRENT MIRRORS 4.5 CURRENT AND VOLTAGE REFERENCES 4.6 BANDGAP REFERENCE 5.1 INVERTERS 5.2 DIFFERENTIAL AMPLIFIERS 5.3 CASCODE AMPLIFIERS 5.4* CURRENT AMPLIFIERS 5.5* OUTPUT AMPLIFIERS/BUFFERS 6.1 DESIGN OF CMOS OP AMPS 6.2 COMPENSATION OF OP AMP 6.3 DESIGN OF TWO-STAGE OP AMPS 6.4 POWER-SUPPLY REJECTION RATIO OF TWO-STAGE OP AMPS 6.5 CASCODE OP AMPS 6.6 SIMULATION AND MEASUREMENT OF OP AMPS 6.7 MACROMODELS FOR OP AMPS 7.1 BUFFERED OP AMPS 7.2 HIGH-SPEED/FREQUENCY OP AMPS 7.3 DIFFERENTIAL-OUTPUT OP AMPS 7.4 MICROPOWER OP AMPS 7.5 LOW NOISE OP AMPS 7.6 LOW VOLTAGE OP AMPS 8.1 CHARACTERIZATION OF A COMPARATOR 8.2 TWO-STAGE, OPEN-LOOP COMPARATOR DESIGN 8.3 OTHER OPEN-LOOP COMPARATORS 8.4 IMPROVING THE PERFORMANCE OF OPEN-LOOP COMPARATORS 8.5 DISCRETE-TIME COMPARATORS 8.6 HIGH-SPEED COMPARATORS APPENDIX A CIRCUIT ANALYSIS FOR ANALOG CIRCUIT DESIGN APPENDIX B INTEGRATED CIRCUIT LAYOUT APPENDIX C CMOS DEVICE CHARACTERIZATION APPENDIX D TIME AND FREQUENCY DOMAIN RELATIONSHIP FOR SECOND-ORDER SYSTEMS
2,741 citations
18 Jun 2007
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Abstract: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time
587 citations
12 Dec 2008
TL;DR: In this paper, a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique is presented, which does not require any amplifiers for the offset voltage cancellation and quiescent current.
Abstract: This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.
378 citations
"A low power preamplifier latch base..." refers background in this paper
...Another approach which was proposed by Kandpal, Varshney and Goswami [4] attained a power dissipation of 71.61µW....
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...Another approach which was proposed by Kandpal, Varshney and Goswami [4] attained a power dissipation of 71....
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TL;DR: In this paper, a dynamic latched comparator with offset voltage compensation is presented, which uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage.
Abstract: A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.
68 citations
TL;DR: Experimental results confirm the ability to reduce the variance of comparator offset by 3600times and to accurately program a desired offset with maximum observed residual offset of 469 muV and standard deviation of 199 mu V.
Abstract: We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-mum CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600times and to accurately program a desired offset with maximum observed residual offset of 469 muV and standard deviation of 199 mu V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1 to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.
46 citations
"A low power preamplifier latch base..." refers background in this paper
...Parameters Ref [10] Ref [11] Ref [8] Ref [12] This Work...
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